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    Searched refs:dwb_pipe_inst (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_stream.c 389 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {
396 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
404 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) {
416 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
427 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
443 uint32_t dwb_pipe_inst)
451 if (dwb_pipe_inst >= MAX_DWB_PIPES) {
456 // stream->writeback_info[dwb_pipe_inst].wb_enabled = false;
460 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_optc.c 313 uint32_t dwb_pipe_inst)
317 if (dwb_pipe_inst == 0)
320 else if (dwb_pipe_inst == 1)
dcn20_hwseq.h 113 unsigned int dwb_pipe_inst);
amdgpu_dcn20_hwseq.c 1761 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1763 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1764 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1768 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1771 mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1781 unsigned int dwb_pipe_inst)
1786 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1787 dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1788 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_stream.h 89 int dwb_pipe_inst; member in struct:dc_writeback_info
352 uint32_t dwb_pipe_inst);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
hw_sequencer.h 160 unsigned int dwb_pipe_inst);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
timing_generator.h 240 uint32_t dwb_pipe_inst);

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