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    Searched refs:dws (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_rlc.c 87 * @dws: the size of save restore block
92 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws)
100 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
132 u32 dws; local
136 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
137 r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
amdgpu_rlc.h 192 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
amdgpu_gfx_v6_0.c 2383 u32 dws; local
2394 dws = adev->gfx.rlc.reg_list_size;
2399 r = amdgpu_gfx_rlc_init_sr(adev, dws);
2407 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2409 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
amdgpu_gfx_v7_0.c 3311 u32 dws; local
3332 dws = adev->gfx.rlc.reg_list_size;
3333 dws += (5 * 16) + 48 + 48 + 64;
3339 r = amdgpu_gfx_rlc_init_sr(adev, dws);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen.c 4162 u32 dws, data, i, j, k, reg_num; local
4169 dws = rdev->rlc.reg_list_size;
4171 dws += (5 * 16) + 48 + 48 + 64;
4178 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true,
4220 for (i = 0; i < dws; i++) {
4223 if (i < dws)
4238 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);
4241 dws = rdev->rlc.clear_state_size + (256 / 4);
4244 dws = 0;
4248 dws += cs_data[i].section[j].reg_count
    [all...]
  /src/sys/dist/pf/net/
pf.c 3824 u_int8_t sws, dws; local
3944 dws = dst->wscale & PF_WSCALE_MASK;
3946 sws = dws = 0;
3991 dws = dst->wscale & PF_WSCALE_MASK;
4014 SEQ_GEQ(end + MAX(1, dst->max_win << dws), src->seqhi))
4015 src->seqhi = end + MAX(1, dst->max_win << dws);
4079 SEQ_GEQ(seq, src->seqlo - (dst->max_win << dws)) &&
4244 SEQ_GEQ(seq, src->seqlo - (dst->max_win << dws)) ?
4581 u_int8_t dws; local
4622 dws = dst->wscale & PF_WSCALE_MASK
    [all...]

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