| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dpm.c | 339 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
350 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
361 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
372 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
385 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
388 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
391 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
393 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
404 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
408 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
726 struct amdgpu_dpm_dynamic_state *dyn_state = &adev->pm.dpm.dyn_state; local
[all...] |
| amdgpu_si_dpm.c | 2261 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2642 &adev->pm.dpm.dyn_state.cac_leakage_table;
3046 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3244 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3251 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3304 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3308 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3309 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3311 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3315 adev->pm.dpm.dyn_state.sclk_mclk_delta)
[all...] |
| amdgpu_kv_dpm.c | 81 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
103 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
910 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
983 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1044 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1110 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1169 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1502 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1538 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table
[all...] |
| amdgpu_dpm.h | 402 struct amdgpu_dpm_dynamic_state dyn_state; member in struct:amdgpu_dpm
|
| amdgpu_atombios.c | 1368 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
1372 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
1384 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_r600_dpm.c | 931 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
940 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
943 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
951 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
954 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
955 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
963 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
966 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
967 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
968 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries)
1305 struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state; local
[all...] |
| radeon_ci_dpm.c | 287 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
289 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
291 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
292 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
295 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
297 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
298 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
299 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
301 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
302 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage)
[all...] |
| radeon_btc_dpm.c | 1236 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values,
1243 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values,
1286 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1290 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
1291 rdev->pm.dpm.dyn_state.mclk_sclk_ratio);
1293 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta)
1297 rdev->pm.dpm.dyn_state.sclk_mclk_delta);
1324 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) {
1326 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta));
1330 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta)
[all...] |
| radeon_ni_dpm.c | 808 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
810 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
885 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
888 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
902 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
905 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
1018 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
1021 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk)
[all...] |
| radeon_si_dpm.c | 2170 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2543 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2946 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3031 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3033 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3053 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3055 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3057 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3159 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3162 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk
[all...] |
| radeon_kv_dpm.c | 562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
584 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
725 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
827 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
900 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
961 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1027 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1086 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1433 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1469 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table
[all...] |
| radeon_rv770_dpm.c | 2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
2265 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
2266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
2267 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_processpptables.c | 1218 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
1219 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
1220 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
1221 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
1222 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
1223 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
1224 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
1225 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
1226 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
1227 hwmgr->dyn_state.ppm_parameter_table = NULL
[all...] |
| amdgpu_smu8_hwmgr.c | 80 hwmgr->dyn_state.vce_clock_voltage_dependency_table;
111 hwmgr->dyn_state.vddc_dependency_on_sclk;
141 hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
267 hwmgr->dyn_state.vddc_dependency_on_sclk;
309 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
410 &hwmgr->dyn_state.max_clock_voltage_on_ac);
449 hwmgr->dyn_state.vddc_dependency_on_sclk;
451 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
453 hwmgr->dyn_state.acp_clock_voltage_dependency_table;
455 hwmgr->dyn_state.uvd_clock_voltage_dependency_table
[all...] |
| amdgpu_smu7_hwmgr.c | 280 hwmgr->dyn_state.mvdd_dependency_on_mclk);
300 hwmgr->dyn_state.vddci_dependency_on_mclk);
325 hwmgr->dyn_state.vddc_dependency_on_mclk);
681 hwmgr->dyn_state.vddc_dependency_on_sclk;
683 hwmgr->dyn_state.vddc_dependency_on_mclk;
685 hwmgr->dyn_state.cac_leakage_table;
735 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
746 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
1846 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
2110 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk
[all...] |
| amdgpu_hwmgr.c | 255 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
256 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
257 hwmgr->dyn_state.max_clock_voltage_on_dc =
258 hwmgr->dyn_state.max_clock_voltage_on_ac;
|
| amdgpu_process_pptables_v1_0.c | 607 hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
609 if (NULL == hwmgr->dyn_state.cac_dtp_table) {
829 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
831 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
833 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
835 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
1143 kfree(hwmgr->dyn_state.cac_dtp_table);
1144 hwmgr->dyn_state.cac_dtp_table = NULL;
|
| amdgpu_vega10_processpptables.c | 1028 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
1030 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
1032 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
1034 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
1271 kfree(hwmgr->dyn_state.cac_dtp_table);
1272 hwmgr->dyn_state.cac_dtp_table = NULL;
|
| amdgpu_smu10_hwmgr.c | 172 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
188 &hwmgr->dyn_state.max_clock_voltage_on_ac);
565 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
566 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
|
| amdgpu_ppatomctrl.c | 1135 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
1136 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) {
1142 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) {
1151 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
|
| amdgpu_vega10_hwmgr.c | 801 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
803 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
805 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
815 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
816 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
3200 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3201 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3230 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
|
| amdgpu_smu_helper.c | 522 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_iceland_smumgr.c | 330 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
381 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
401 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
403 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
405 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
409 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
410 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
411 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
545 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk
[all...] |
| amdgpu_ci_smumgr.c | 422 hwmgr->dyn_state.vddc_dependency_on_sclk, clock,
434 hwmgr->dyn_state.vddc_phase_shed_limits_table,
535 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
588 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
590 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
592 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
595 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
597 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
598 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| hwmgr.h | 773 struct phm_dynamic_state_info dyn_state; member in struct:pp_hwmgr
|
