| /src/sys/arch/arm/samsung/ |
| exynos5410_clock.c | 521 struct exynos_clk *eclk)
527 switch (eclk->type) {
545 clk_parent = exynos5410_clock_get_parent(sc, &eclk->base);
549 eclk->base.name,
552 type, clk_get_rate(&eclk->base));
559 struct exynos_clk *eclk; local in function:exynos5410_clock_decode
568 eclk = exynos5410_clock_find_by_id(clock_id);
569 if (eclk)
570 return &eclk->base;
577 struct exynos_clk *eclk)
721 struct exynos_clk *eclk; local in function:exynos5410_clock_get
735 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5410_clock_put
745 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5410_clock_get_rate
767 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5410_clock_set_rate
790 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5410_clock_enable
810 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5410_clock_disable
830 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5410_clock_set_parent
849 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5410_clock_get_parent
[all...] |
| exynos5422_clock.c | 698 struct exynos_clk *eclk)
704 switch (eclk->type) {
722 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base);
726 eclk->base.name,
729 type, clk_get_rate(&eclk->base));
736 struct exynos_clk *eclk; local in function:exynos5422_clock_decode
745 eclk = exynos5422_clock_find_by_id(clock_id);
746 if (eclk)
747 return &eclk->base;
754 struct exynos_clk *eclk)
898 struct exynos_clk *eclk; local in function:exynos5422_clock_get
912 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5422_clock_put
922 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5422_clock_get_rate
944 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5422_clock_set_rate
967 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5422_clock_enable
987 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5422_clock_disable
1007 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5422_clock_set_parent
1026 struct exynos_clk *eclk = (struct exynos_clk *)clk; local in function:exynos5422_clock_get_parent
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| hwmgr_ppt.h | 63 uint32_t eclk; /* VCE clock */ member in struct:phm_ppt_v1_mm_clock_voltage_dependency_record
|
| amdgpu_process_pptables_v1_0.c | 726 mm_table_record->eclk = le32_to_cpu(mm_dependency_record->ulEClk);
|
| amdgpu_vega10_processpptables.c | 374 mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk);
|
| amdgpu_vega10_hwmgr.c | 1380 dep_mm_table->entries[i].eclk) {
1382 dep_mm_table->entries[i].eclk;
1946 "Failed to get ECLK clock settings from VBIOS!",
1952 if (dep_table->entries[i].eclk == eclock)
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| ecx-common.dtsi | 42 clocks = <&eclk>;
180 eclk: eclk { label
|
| aspeed-g4.dtsi | 232 clock-names = "vclk", "eclk";
|
| aspeed-g5.dtsi | 297 clock-names = "vclk", "eclk";
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 67 struct dm_pp_clock_range eclk; member in struct:dm_pp_gpu_clock_range
|
| /src/sys/external/bsd/drm2/dist/include/uapi/drm/ |
| amdgpu_drm.h | 1047 __u32 eclk; member in struct:drm_amdgpu_info_vce_clock_table_entry
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| amdgpu_smu.h | 218 uint32_t eclk; member in struct:smu_bios_boot_up_values
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_kms.c | 785 vce_clk_table.entries[i].eclk = vce_state->evclk;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_smu_v11_0.c | 613 smu->smu_table.boot_values.eclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
|
| amdgpu_vega20_ppt.c | 161 CLK_MAP(ECLK, PPCLK_ECLK),
779 /* eclk */
785 pr_err("[SetupDefaultDpmTable] failed to get eclk dpm levels!");
790 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.eclk / 100;
2218 /* eclk */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_fiji_smumgr.c | 1440 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
|
| amdgpu_vegam_smumgr.c | 1213 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
|
| amdgpu_polaris10_smumgr.c | 1308 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
|
| amdgpu_tonga_smumgr.c | 1390 mm_table->entries[count].eclk;
|
