| /src/sys/arch/powerpc/pic/ |
| i8259_common.c | 73 i8259->enable_mask = ~i8259->irqs;
74 isa_outb(IO_ICU1+1, i8259->enable_mask);
75 isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);
84 i8259->enable_mask |= mask;
85 isa_outb(IO_ICU1+1, i8259->enable_mask);
86 isa_outb(IO_ICU2+1, i8259->enable_mask >> 8);
|
| pic_i8259.c | 72 i8259->enable_mask = 0xffffffff;
|
| picvar.h | 85 uint32_t enable_mask; member in struct:i8259_ops
|
| pic_prepivr.c | 91 prepivr->enable_mask = 0xffffffff;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_gt_pm_irq.h | 19 void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask);
|
| intel_gt_pm_irq.c | 98 void gen6_gt_pm_enable_irq(struct intel_gt *gt, u32 enable_mask)
102 gt->pm_ier |= enable_mask;
104 gen6_gt_pm_unmask_irq(gt, enable_mask);
|
| /src/sys/dev/i2c/ |
| rkpmic.c | 81 uint8_t enable_mask; member in struct:rkpmic_ctrl
102 .enable_reg = 0x23, .enable_mask = __BIT(0),
106 .enable_reg = 0x23, .enable_mask = __BIT(1),
110 .enable_reg = 0x23, .enable_mask = __BIT(2) },
112 .enable_reg = 0x23, .enable_mask = __BIT(3),
118 .enable_reg = 0x27, .enable_mask = __BIT(0),
122 .enable_reg = 0x27, .enable_mask = __BIT(1),
126 .enable_reg = 0x27, .enable_mask = __BIT(2),
140 .enable_reg = 0x23, .enable_mask = __BIT(0),
144 .enable_reg = 0x23, .enable_mask = __BIT(1)
[all...] |
| as3722.c | 136 u_int enable_mask; member in struct:as3722regdef
149 .enable_mask = AS3722_SDCONTROL_SD4_ENABLE,
156 .enable_mask = 0x40,
581 if (!regdef->enable_mask)
587 regdef->enable_mask, 0, flags);
590 0, regdef->enable_mask, flags);
|
| /src/sys/arch/macppc/macppc/ |
| pic_ohare.c | 57 uint32_t enable_mask; member in struct:ohare_ops
147 ohare->enable_mask = 0;
170 ohare->enable_mask |= mask;
171 out32rb(INT_ENABLE_REG, ohare->enable_mask);
181 ohare->enable_mask |= mask;
182 out32rb(INT_ENABLE_REG, ohare->enable_mask);
196 ohare->enable_mask &= ~mask;
197 out32rb(INT_ENABLE_REG, ohare->enable_mask);
209 levels = in32rb(INT_LEVEL_REG) & ohare->enable_mask;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
| irq_service.h | 52 uint32_t enable_mask; member in struct:irq_source_info
|
| amdgpu_irq_service.c | 102 value = (value & ~info->enable_mask) |
103 (info->enable_value[enable ? 0 : 1] & info->enable_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 99 .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK,\
114 .enable_mask = DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK,\
127 .enable_mask =\
142 .enable_mask =\
158 .enable_mask =\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/ |
| amdgpu_irq_service_dce80.c | 102 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\
117 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\
131 .enable_mask =\
146 .enable_mask =\
162 .enable_mask =\
|
| /src/sys/arch/powerpc/marvell/ |
| pic_discovery.c | 65 #define enable_mask _mask.mask64 macro
108 discovery->enable_mask = 0;
118 discovery->enable_mask |= (1 << irq);
127 discovery->enable_mask &= ~(1 << irq);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_fifo_underrun.c | 99 u32 enable_mask; local in function:i9xx_check_fifo_underruns
106 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);
107 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
124 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); local in function:i9xx_set_fifo_underrun_reporting
126 I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS);
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen_hdmi.c | 44 u8 enable_mask)
51 if (enable_mask) {
53 if (enable_mask & 1)
55 if (enable_mask & 2)
57 if (enable_mask & 4)
59 if (enable_mask & 8)
|
| radeon_r600_hdmi.c | 148 u8 enable_mask)
155 if (enable_mask) {
157 if (enable_mask & 1)
159 if (enable_mask & 2)
161 if (enable_mask & 4)
163 if (enable_mask & 8)
|
| kv_dpm.h | 68 u32 enable_mask; member in struct:kv_lcac_config_reg
191 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
|
| radeon_kv_smc.c | 58 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask)
65 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);
|
| radeon_audio.h | 43 struct r600_audio_pin *pin, u8 enable_mask);
|
| radeon_dce6_afmt.c | 264 u8 enable_mask)
270 enable_mask ? AUDIO_ENABLED : 0);
|
| radeon_audio.c | 38 u8 enable_mask);
40 u8 enable_mask);
42 u8 enable_mask);
251 struct r600_audio_pin *pin, u8 enable_mask)
271 if ((pin_count > 1) && (enable_mask == 0))
276 rdev->audio.funcs->enable(rdev, pin, enable_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_kv_smc.c | 61 int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask)
68 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0);
|
| kv_dpm.h | 94 u32 enable_mask; member in struct:kv_lcac_config_reg
220 int amdgpu_kv_dpm_get_enable_mask(struct amdgpu_device *adev, u32 *enable_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_irq.c | 422 u32 enable_mask = status_mask << 16; local in function:i915_pipestat_enable_mask
442 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
446 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
448 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
451 WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
453 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
454 pipe_name(pipe), enable_mask, status_mask);
456 return enable_mask;
463 u32 enable_mask; local in function:i915_enable_pipestat
476 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe)
486 u32 enable_mask; local in function:i915_disable_pipestat
1314 u32 status_mask, enable_mask, iir_bit = 0; local in function:i9xx_pipestat_irq_ack
2732 u32 enable_mask; local in function:vlv_display_irq_postinstall
3500 u16 enable_mask; local in function:i8xx_irq_postinstall
3667 u32 enable_mask; local in function:i915_irq_postinstall
3773 u32 enable_mask; local in function:i965_irq_postinstall
[all...] |
