/src/sys/arch/sun3/sun3x/ |
enable.c | 44 volatile short *enable_reg; variable in typeref:typename:volatile short * 52 enable_reg = (void *)va; 67 ena = *enable_reg; 74 *enable_reg = ena; 85 ena = *enable_reg; 92 *enable_reg = ena;
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enable.h | 59 extern volatile short *enable_reg;
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dvma.c | 127 *enable_reg |= ENA_SDVMA;
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/src/sys/dev/i2c/ |
rkpmic.c | 80 uint8_t enable_reg; member in struct:rkpmic_ctrl 102 .enable_reg = 0x23, .enable_mask = __BIT(0), 106 .enable_reg = 0x23, .enable_mask = __BIT(1), 110 .enable_reg = 0x23, .enable_mask = __BIT(2) }, 112 .enable_reg = 0x23, .enable_mask = __BIT(3), 118 .enable_reg = 0x27, .enable_mask = __BIT(0), 122 .enable_reg = 0x27, .enable_mask = __BIT(1), 126 .enable_reg = 0x27, .enable_mask = __BIT(2), 140 .enable_reg = 0x23, .enable_mask = __BIT(0), 144 .enable_reg = 0x23, .enable_mask = __BIT(1) [all...] |
as3722.c | 135 u_int enable_reg; member in struct:as3722regdef 148 .enable_reg = AS3722_SDCONTROL_REG, 155 .enable_reg = AS3722_LDOCONTROL0_REG, 586 error = as3722_set_clear(asc, regdef->enable_reg, 589 error = as3722_set_clear(asc, regdef->enable_reg,
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
amdgpu_irq_service_dce110.c | 60 value = dm_read_reg(irq_service->ctx, info->enable_reg); 66 dm_write_reg(irq_service->ctx, info->enable_reg, value); 98 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 113 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\ 126 .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\ 141 .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\ 157 .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/ |
amdgpu_irq_service_dce80.c | 61 value = dm_read_reg(irq_service->ctx, info->enable_reg); 69 dm_write_reg(irq_service->ctx, info->enable_reg, value); 101 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 116 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 130 .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\ 145 .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\ 161 .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
irq_service.h | 51 uint32_t enable_reg; member in struct:irq_source_info
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amdgpu_irq_service.c | 99 uint32_t addr = info->enable_reg;
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/src/sys/arch/arm/sunxi/ |
sunxi_nmi.c | 60 /* enable_reg */ 67 bus_size_t enable_reg; member in struct:sunxi_nmi_config 74 .enable_reg = 0x08, 81 .enable_reg = 0x40, 88 .enable_reg = 0x08, 139 val = NMI_READ(sc, sc->sc_config->enable_reg); 144 NMI_WRITE(sc, sc->sc_config->enable_reg, val);
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
amdgpu_irq_service_dce120.c | 61 value = dm_read_reg(irq_service->ctx, info->enable_reg); 69 dm_write_reg(irq_service->ctx, info->enable_reg, value); 111 .enable_reg = SRI(reg1, block, reg_num),\
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
amdgpu_irq_service_dcn10.c | 142 value = dm_read_reg(irq_service->ctx, info->enable_reg); 150 dm_write_reg(irq_service->ctx, info->enable_reg, value); 192 .enable_reg = SRI(reg1, block, reg_num),\
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
amdgpu_irq_service_dcn20.c | 142 value = dm_read_reg(irq_service->ctx, info->enable_reg); 150 dm_write_reg(irq_service->ctx, info->enable_reg, value); 194 .enable_reg = SRI(reg1, block, reg_num),\
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
amdgpu_irq_service_dcn21.c | 143 value = dm_read_reg(irq_service->ctx, info->enable_reg); 151 dm_write_reg(irq_service->ctx, info->enable_reg, value); 190 .enable_reg = SRI(reg1, block, reg_num),\
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/src/sys/external/bsd/drm2/dist/drm/i915/display/ |
intel_dpll_mgr.c | 3272 i915_reg_t enable_reg) 3284 val = I915_READ(enable_reg); 3311 i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); local in function:combo_pll_get_hw_state 3315 enable_reg = MG_PLL_ENABLE(0); 3318 return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); 3474 i915_reg_t enable_reg) 3478 val = I915_READ(enable_reg); 3480 I915_WRITE(enable_reg, val); 3486 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1)) 3492 i915_reg_t enable_reg) 3508 i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); local in function:combo_pll_enable 3559 i915_reg_t enable_reg = local in function:mg_pll_enable 3619 i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id); local in function:combo_pll_disable 3643 i915_reg_t enable_reg = local in function:mg_pll_disable [all...] |