| /src/external/gpl3/gcc/dist/libgcc/config/sparc/ |
| crtfastmath.c | 30 unsigned int fsr; local
33 the fsr register modified the upper 32-bit, the only thing up there
37 __asm__("st %%fsr, %0"
38 : "=m" (fsr));
40 fsr |= FPRS_NS;
42 __asm__("ld %0, %%fsr"
43 : : "m" (fsr));
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/sparc/ |
| crtfastmath.c | 30 unsigned int fsr; local
33 the fsr register modified the upper 32-bit, the only thing up there
37 __asm__("st %%fsr, %0"
38 : "=m" (fsr));
40 fsr |= FPRS_NS;
42 __asm__("ld %0, %%fsr"
43 : : "m" (fsr));
|
| /src/sys/arch/sparc64/include/ |
| fsr.h | 1 /* $NetBSD: fsr.h,v 1.4 2010/08/08 18:44:16 chs Exp $ */
3 #include <sparc/fsr.h>
|
| reg.h | 160 #include <machine/fsr.h>
188 int64_t fr_fsr; /* %fsr */
206 int fr_fsr; /* %fsr */
|
| /src/external/gpl3/gdb.old/dist/sim/erc32/ |
| float.c | 25 3. Propagate any exceptions to the simulated FSR.
63 /* How to map SPARC FSR onto the host */
65 set_fsr(uint32_t fsr)
69 fsr >>= 30;
70 switch (fsr) {
|
| exec.c | 551 fcc = (sregs->fsr >> 10) & 0x3;
1407 sregs->fsr =
1408 (sregs->fsr & 0x7FF000) | (data & ~0x7FF000);
1409 set_fsr(sregs->fsr);
1424 mexc = memory_write(asi, address, &sregs->fsr, 2, &ws);
1494 if (!(sregs->fsr & FSR_QNE)) {
1495 sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR;
1509 sregs->fsr &= ~FSR_QNE;
1682 sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR
[all...] |
| /src/external/gpl3/gdb/dist/sim/erc32/ |
| float.c | 25 3. Propagate any exceptions to the simulated FSR.
63 /* How to map SPARC FSR onto the host */
65 set_fsr(uint32_t fsr)
69 fsr >>= 30;
70 switch (fsr) {
|
| exec.c | 551 fcc = (sregs->fsr >> 10) & 0x3;
1407 sregs->fsr =
1408 (sregs->fsr & 0x7FF000) | (data & ~0x7FF000);
1409 set_fsr(sregs->fsr);
1424 mexc = memory_write(asi, address, &sregs->fsr, 2, &ws);
1494 if (!(sregs->fsr & FSR_QNE)) {
1495 sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR;
1509 sregs->fsr &= ~FSR_QNE;
1682 sregs->fsr = (sregs->fsr & ~FSR_TT) | FP_SEQ_ERR
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.arch/ |
| sparc64-regs.S | 80 ldx [%l0], %fsr
81 sllx %l1, 1, %l1 ! sparc64-regs.exp: after first %fsr
83 ldx [%l0], %fsr
86 ldx [%l0], %fsr
89 ldx [%l0], %fsr
92 ldx [%l0], %fsr
95 ldx [%l0], %fsr
98 ldx [%l0], %fsr
101 ldx [%l0], %fsr
104 ldx [%l0], %fsr
[all...] |
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.arch/ |
| sparc64-regs.S | 80 ldx [%l0], %fsr
81 sllx %l1, 1, %l1 ! sparc64-regs.exp: after first %fsr
83 ldx [%l0], %fsr
86 ldx [%l0], %fsr
89 ldx [%l0], %fsr
92 ldx [%l0], %fsr
95 ldx [%l0], %fsr
98 ldx [%l0], %fsr
101 ldx [%l0], %fsr
104 ldx [%l0], %fsr
[all...] |
| /src/sys/arch/sparc64/sparc64/ |
| netbsd32_sigcode.s | 31 #include <machine/fsr.h>
|
| sigcode32.s | 100 * Make room on the stack for 32 %f registers + %fsr. This comes
121 st %fsr, [%sp + CCFSZ + 0]
152 ld [%sp + CCFSZ + 0], %fsr
|
| /src/lib/libc/arch/sparc64/gen/ |
| modf.S | 47 #include <machine/fsr.h>
74 * 4@[%fp + BIAS - 4] saved %fsr
75 * 4@[%fp + BIAS - 8] new %fsr with rounding set to `towards 0'
126 st %fsr, [%fp + BIAS - 4] ! %l5 = current FSR mode
134 ld [%fp + BIAS - 8], %fsr
140 * Restore %fsr, but leave exceptions accrued.
142 st %fsr, [%fp + BIAS - 4]
144 andn %l6, %l3, %l6 ! %l6 = %fsr & ~FSR_RD;
147 ld [%fp + BIAS - 4], %fsr ! restore %fsr, leaving accrued stuf
[all...] |
| /src/lib/libc/arch/sparc/gen/ |
| modf.S | 47 #include <machine/fsr.h>
74 * 4@[%fp - 4] saved %fsr
75 * 4@[%fp - 8] new %fsr with rounding set to `towards 0'
131 st %fsr, [%fp - 4] ! %l5 = current FSR mode
139 ld [%fp - 8], %fsr
145 * Restore %fsr, but leave exceptions accrued.
147 st %fsr, [%fp - 4]
149 andn %l6, %l3, %l6 ! %l6 = %fsr & ~FSR_RD;
152 ld [%fp - 4], %fsr ! restore %fsr, leaving accrued stuf
[all...] |
| /src/sys/arch/arm/arm32/ |
| fault.c | 190 data_abort_fixup(trapframe_t *tf, u_int fsr, u_int far, struct lwp *l)
221 dab_fatal(tf, fsr, far, l, NULL);
235 u_int far, fsr; local
245 /* Grab FAR/FSR before enabling interrupts */
247 fsr = cpu_faultstatus();
264 UVMHIST_LOG(maphist, " (l=%#jx, far=%#jx, fsr=%#jx",
265 (uintptr_t)l, far, fsr, 0);
275 curcpu()->ci_abt_evs[fsr & FAULT_TYPE_MASK].ev_count++;
278 if (__predict_false(data_aborts[fsr & FAULT_TYPE_MASK].func != NULL)) {
280 printf("%s: data_aborts fsr=0x%x far=0x%x\n"
[all...] |
| /src/sys/arch/sparc/include/ |
| reg.h | 88 #include <machine/fsr.h>
108 int fr_fsr; /* %fsr */
|
| /src/tests/fs/lfs/ |
| t_fcntl.c | 203 struct lfs_filestat_req fsr; local
223 fsr.ino = ino;
224 fsr.len = 1;
225 fsr.fss = &fss_before;
226 if (rump_sys_fcntl(fd, LFCNFILESTATS, &fsr) < 0)
239 fsr.fss = &fss_scrambled;
240 if (rump_sys_fcntl(fd, LFCNFILESTATS, &fsr) < 0)
254 fsr.fss = &fss_after;
255 if (rump_sys_fcntl(fd, LFCNFILESTATS, &fsr) < 0)
|
| /src/sys/arch/sparc/fpu/ |
| fpu.c | 138 int i, fsr = fs->fs_fsr, error; local
154 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) {
163 if ((i = fsr & FSR_CX) == 0)
198 printf("fsr=0x%x\n", fsr);
305 int opf, rs1, rs2, rd, type, mask, fsr, cx; local
308 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; local
537 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT);
539 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) {
540 fs->fs_fsr = (fsr & ~FSR_FTT)
[all...] |
| /src/lib/libc/compat/arch/sparc64/sys/ |
| compat___sigtramp1.S | 54 #include <machine/fsr.h>
88 * Make room on the stack for 64 %f registers + %fsr. This comes
111 stx %fsr, [%sp + CC64FSZ + BIAS + 0]
143 ldx [%sp + CC64FSZ + BIAS + 0], %fsr
|
| /src/sys/arch/arm/sunxi/ |
| sun6i_spi.c | 323 uint32_t fsr; local
328 fsr = SPIREG_READ(sc, SPI_FSR);
329 if (__SHIFTOUT(fsr, SPI_FSR_TF_CNT) >= 64) {
348 uint32_t fsr; local
353 fsr = SPIREG_READ(sc, SPI_FSR);
354 if (__SHIFTOUT(fsr, SPI_FSR_RF_CNT) == 0) {
|
| /src/sys/arch/sparc/sparc/ |
| sigcode_state.s | 90 * Make room on the stack for 32 %f registers + %fsr. This comes \
102 * Saving the fpu registers is expensive, so do it iff the fsr \
111 st %fsr, [%sp + CCFSZ + 0]; \
138 ld [%sp + CCFSZ + 0], %fsr; \
|
| /src/external/gpl3/gdb.old/dist/sim/frv/ |
| frv-sim.h | 339 /* Floating point trap types for FSR. */
352 enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
507 /* The FSR registers.
512 #define SET_FSR(index, fsr) \
513 (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
515 #define GET_FSR_TEM(fsr) ( \
516 ((fsr) >> 24) & 0x3f \
519 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
520 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1
[all...] |
| /src/external/gpl3/gdb/dist/sim/frv/ |
| frv-sim.h | 339 /* Floating point trap types for FSR. */
352 enum frv_fsr_traps fsr_mask; /* interrupt code for FSR */
507 /* The FSR registers.
512 #define SET_FSR(index, fsr) \
513 (CPU (h_spr[H_SPR_FSR0 + (index)]) = (fsr))
515 #define GET_FSR_TEM(fsr) ( \
516 ((fsr) >> 24) & 0x3f \
519 #define SET_FSR_QNE(fsr) ((fsr) |= (1 << 20))
520 #define GET_FSR_QNE(fsr) (((fsr) >> 20) & 1
[all...] |
| /src/sys/arch/powerpc/fpu/ |
| fpu_emu.c | 349 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr, cond; local
838 fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX);
840 fsr |= cx;
841 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr));
843 if (fsr & FPSR_INV)
844 fsr |= FPSCR_VX;
845 mask = (fsr & FPSR_EX) << (25 - 3);
846 if (fsr & mask)
847 fsr |= FPSCR_FEX
[all...] |
| /src/lib/libc/compat/arch/sparc/sys/ |
| compat___sigtramp1.S | 82 * Make room on the stack for 32 %f registers + %fsr. This comes \
94 * Saving the fpu registers is expensive, so do it iff the fsr \
103 st %fsr, [%sp + CCFSZ + 0]; \
130 ld [%sp + CCFSZ + 0], %fsr; \
|
