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    Searched refs:hpd_offsets (Results 1 - 4 of 4) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 69 static const u32 hpd_offsets[] = variable
294 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
318 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
323 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
355 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
357 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
361 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
363 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
365 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
372 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)
    [all...]
amdgpu_dce_v11_0.c 69 static const u32 hpd_offsets[] = variable
312 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
336 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
373 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
375 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
379 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
381 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
383 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
390 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)
    [all...]
amdgpu_dce_v6_0.c 72 static const u32 hpd_offsets[] = variable
246 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
269 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
274 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
299 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
301 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
310 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
312 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
344 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
346 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0)
    [all...]
amdgpu_dce_v8_0.c 69 static const u32 hpd_offsets[] = variable
239 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
263 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
268 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
293 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
295 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
304 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
306 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
338 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
340 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0)
    [all...]

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