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  /src/sys/arch/vax/vax/
db_disasm.c 115 static inline int get_byte(inst_buffer * ib);
116 static inline int get_word(inst_buffer * ib);
117 static inline int get_long(inst_buffer * ib);
119 static int get_opcode(inst_buffer * ib);
120 static int get_operands(inst_buffer * ib);
121 static int get_operand(inst_buffer * ib, int size);
123 static inline void add_char(inst_buffer * ib, char c);
124 static inline void add_str(inst_buffer * ib, const char *s);
125 static void add_int(inst_buffer * ib, int i);
126 static void add_xint(inst_buffer * ib, int i)
148 inst_buffer ib; local in function:db_disasm
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opcodes.c 445 get_byte(long ib)
447 return *((u_int8_t *)ib);
451 skip_opcode(long ib)
457 opc = get_byte(ib++);
461 opc += get_byte(ib++);
467 return ib;
475 ib++;
478 ib += 2;
481 ib += 4;
512 ib = skip_operand(ib, size)
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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si_dma.c 67 * @ib: indirect buffer to fill with commands
75 struct radeon_ib *ib,
84 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY,
86 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
87 ib->ptr[ib->length_dw++] = lower_32_bits(src);
88 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff
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radeon_ni_dma.c 120 * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine
123 * @ib: IB object to schedule
125 * Schedule an IB in the DMA ring (cayman-SI).
128 struct radeon_ib *ib)
130 struct radeon_ring *ring = &rdev->ring[ib->ring];
131 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
150 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0))
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radeon_ib.c 41 * IB
43 * commands are stored. You can put a pointer to the IB in the
44 * command ring and the hw will fetch the commands from the IB
52 * radeon_ib_get - request an IB (Indirect Buffer)
55 * @ring: ring index the IB is associated with
56 * @ib: IB object returned
57 * @size: requested IB size
59 * Request an IB (all asics). IBs are allocated using the
64 struct radeon_ib *ib, struct radeon_vm *vm
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radeon_vce.c 407 struct radeon_ib ib; local in function:radeon_vce_get_create_msg
411 r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
413 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
417 dummy = ib.gpu_addr + 1024;
420 ib.length_dw = 0;
421 ib.ptr[ib.length_dw++] = cpu_to_le32(0x0000000c); /* len */
422 ib.ptr[ib.length_dw++] = cpu_to_le32(0x00000001); /* session cmd */
423 ib.ptr[ib.length_dw++] = cpu_to_le32(handle)
474 struct radeon_ib ib; local in function:radeon_vce_get_destroy_msg
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radeon_cik_sdma.c 131 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
134 * @ib: IB object to schedule
136 * Schedule an IB in the DMA ring (CIK).
139 struct radeon_ib *ib)
141 struct radeon_ring *ring = &rdev->ring[ib->ring];
142 u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;
156 /* IB packet must end on a 8 DW boundary *
709 struct radeon_ib ib; local in function:cik_sdma_ib_test
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radeon_vm.c 356 * @ib: indirect buffer to fill with commands
367 struct radeon_ib *ib,
376 radeon_asic_vm_copy_pages(rdev, ib, pe, src, count);
379 radeon_asic_vm_write_pages(rdev, ib, pe, addr,
383 radeon_asic_vm_set_pages(rdev, ib, pe, addr,
398 struct radeon_ib ib; local in function:radeon_vm_clear_bo
414 r = radeon_ib_get(rdev, R600_RING_TYPE_DMA_INDEX, &ib, NULL, 256);
418 ib.length_dw = 0;
420 radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
421 radeon_asic_vm_pad_ib(rdev, &ib);
656 struct radeon_ib ib; local in function:radeon_vm_update_page_directory
924 struct radeon_ib ib; local in function:radeon_vm_bo_update
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radeon_r600_cs.c 362 volatile u32 *ib = p->ib.ptr; local in function:r600_cs_track_validate_cb
472 ib[track->cb_color_size_idx[i]] = tmp;
531 volatile u32 *ib = p->ib.ptr; local in function:r600_cs_track_validate_db
569 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
838 volatile uint32_t *ib; local in function:r600_cs_common_vline_parse
840 ib = p->ib.ptr;
903 ib[h_idx + 2] = PACKET2(0)
976 u32 m, i, tmp, *ib; local in function:r600_cs_check_reg
1634 volatile u32 *ib; local in function:r600_packet3_check
2384 volatile u32 *ib = p->ib.ptr; local in function:r600_dma_cs_parse
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radeon_evergreen_cs.c 460 uint32_t *ib = p->ib.ptr; local in function:evergreen_cs_track_validate_cb
482 ib[track->cb_color_slice_idx[id]] = slice;
1087 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1127 u32 tmp, *ib; local in function:evergreen_cs_handle_reg
1130 ib = p->ib.ptr;
1160 /* get value to populate the IB don't remove */
1162 ib[idx] = 0;*/
1178 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff)
1806 uint32_t *ib; local in function:evergreen_packet3_check
2831 uint32_t *ib = p->ib.ptr; local in function:evergreen_dma_cs_parse
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  /src/sys/dev/ic/
igpio.c 162 igpio_find_bank_setup(struct igpio_bank *ib, int barno)
167 if (strcmp(ib->ib_sc->sc_acpi_hid, ibs->ibs_acpi_hid) != 0)
182 struct igpio_bank *ib; local in function:igpio_find_bank
185 ib = &sc->sc_banks[i];
186 if (pin >= ib->ib_setup->ibs_first_pin &&
187 pin <= ib->ib_setup->ibs_last_pin)
191 ib = NULL;
193 return ib;
197 igpio_bank_pin(struct igpio_bank *ib, int pin)
199 return pin - ib->ib_setup->ibs_first_pin
236 struct igpio_bank *ib = &sc->sc_banks[i]; local in function:igpio_attach
379 struct igpio_bank *ib = &sc->sc_banks[i]; local in function:igpio_detach
470 struct igpio_bank *ib = igpio_find_bank(sc, pin); local in function:igpio_pin_read
497 struct igpio_bank *ib = igpio_find_bank(sc, pin); local in function:igpio_pin_write
529 struct igpio_bank *ib = igpio_find_bank(sc, pin); local in function:igpio_pin_ctl
605 struct igpio_bank *ib = igpio_find_bank(sc, pin); local in function:igpio_intr_establish
682 struct igpio_bank *ib; local in function:igpio_intr_disestablish
743 struct igpio_bank *ib = &sc->sc_banks[i]; local in function:igpio_intr
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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_sdma_v2_4.c 249 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
252 * @ib: IB object to schedule
254 * Schedule an IB in the DMA ring (VI).
258 struct amdgpu_ib *ib,
263 /* IB packet must end on a 8 DW boundary */
269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
271 amdgpu_ring_write(ring, ib->length_dw);
598 * sdma_v2_4_ring_test_ib - test an IB on the DMA engin
608 struct amdgpu_ib ib; local in function:sdma_v2_4_ring_test_ib
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amdgpu_vce.c 451 struct amdgpu_ib *ib; local in function:amdgpu_vce_get_create_msg
460 ib = &job->ibs[0];
465 ib->length_dw = 0;
466 ib->ptr[ib->length_dw++] = 0x0000000c; /* len */
467 ib->ptr[ib->length_dw++] = 0x00000001; /* session cmd */
468 ib->ptr[ib->length_dw++] = handle;
471 ib->ptr[ib->length_dw++] = 0x00000040; /* len *
530 struct amdgpu_ib *ib; local in function:amdgpu_vce_get_destroy_msg
725 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; local in function:amdgpu_vce_ring_parse_cs
961 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; local in function:amdgpu_vce_ring_parse_cs_vm
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amdgpu_si_dma.c 70 struct amdgpu_ib *ib,
80 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
81 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
250 * si_dma_ring_test_ib - test an IB on the DMA engine
254 * Test a simple IB in the DMA ring (VI).
260 struct amdgpu_ib ib; local in function:si_dma_ring_test_ib
274 memset(&ib, 0, sizeof(ib));
275 r = amdgpu_ib_get(adev, NULL, 256, &ib);
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amdgpu_cik_sdma.c 220 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
223 * @ib: IB object to schedule
225 * Schedule an IB in the DMA ring (CIK).
229 struct amdgpu_ib *ib,
235 /* IB packet must end on a 8 DW boundary */
239 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
240 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
241 amdgpu_ring_write(ring, ib->length_dw);
662 * cik_sdma_ring_test_ib - test an IB on the DMA engin
672 struct amdgpu_ib ib; local in function:cik_sdma_ring_test_ib
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amdgpu_sdma.h 89 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
104 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
113 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
114 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
amdgpu_vcn.c 394 struct amdgpu_ib *ib; local in function:amdgpu_vcn_dec_send_msg
402 ib = &job->ibs[0];
404 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
405 ib->ptr[1] = addr;
406 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
407 ib->ptr[3] = addr >> 32;
408 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
409 ib->ptr[5] = 0;
411 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
412 ib->ptr[i+1] = 0
562 struct amdgpu_ib *ib; local in function:amdgpu_vcn_enc_get_create_msg
615 struct amdgpu_ib *ib; local in function:amdgpu_vcn_enc_get_destroy_msg
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amdgpu_sdma_v3_0.c 423 * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
426 * @ib: IB object to schedule
428 * Schedule an IB in the DMA ring (VI).
432 struct amdgpu_ib *ib,
437 /* IB packet must end on a 8 DW boundary */
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
445 amdgpu_ring_write(ring, ib->length_dw);
870 * sdma_v3_0_ring_test_ib - test an IB on the DMA engin
880 struct amdgpu_ib ib; local in function:sdma_v3_0_ring_test_ib
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amdgpu_sdma_v5_0.c 377 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
380 * @ib: IB object to schedule
382 * Schedule an IB in the DMA ring (NAVI10).
386 struct amdgpu_ib *ib,
392 /* An IB packet must end on a 8 DW boundary--the next dword
393 * must be on a 8-dword boundary. Our IB packet below is 6
405 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
406 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
407 amdgpu_ring_write(ring, ib->length_dw)
943 struct amdgpu_ib ib; local in function:sdma_v5_0_ring_test_ib
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amdgpu_uvd_v6_0.c 219 struct amdgpu_ib *ib; local in function:uvd_v6_0_enc_get_create_msg
228 ib = &job->ibs[0];
231 ib->length_dw = 0;
232 ib->ptr[ib->length_dw++] = 0x00000018;
233 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
234 ib->ptr[ib->length_dw++] = handle;
235 ib->ptr[ib->length_dw++] = 0x00010000
282 struct amdgpu_ib *ib; local in function:uvd_v6_0_enc_get_destroy_msg
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amdgpu_ib.c 48 * IB
50 * commands are stored. You can put a pointer to the IB in the
51 * command ring and the hw will fetch the commands from the IB
59 * amdgpu_ib_get - request an IB (Indirect Buffer)
61 * @ring: ring index the IB is associated with
62 * @size: requested IB size
63 * @ib: IB object returned
65 * Request an IB (all asics). IBs are allocated using the
70 unsigned size, struct amdgpu_ib *ib)
132 struct amdgpu_ib *ib = &ibs[0]; local in function:amdgpu_ib_schedule
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amdgpu_jpeg.c 147 struct amdgpu_ib *ib; local in function:amdgpu_jpeg_dec_set_reg
156 ib = &job->ibs[0];
158 ib->ptr[0] = PACKETJ(adev->jpeg.internal.jpeg_pitch, 0, 0, PACKETJ_TYPE0);
159 ib->ptr[1] = 0xDEADBEEF;
161 ib->ptr[i] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
162 ib->ptr[i+1] = 0;
164 ib->length_dw = 16;
  /src/sys/arch/hppa/hppa/
intr.c 130 struct hppa_interrupt_bit *ib; local in function:hppa_intr_establish
180 ib = &ci->ci_ib[idx];
183 ib->ib_reg = ir;
184 ib->ib_ipl = ipl;
185 ib->ib_spl = (1 << idx);
186 snprintf(ib->ib_name, sizeof(ib->ib_name), "irq %d", bit_pos);
188 evcnt_attach_dynamic(&ib->ib_evcnt, EVCNT_TYPE_INTR, NULL, ir->ir_name,
189 ib->ib_name);
190 ib->ib_handler = handler
254 struct hppa_interrupt_bit *ib; local in function:hppa_intr_calculatemasks
405 struct hppa_interrupt_bit *ib; local in function:hppa_intr_dispatch
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  /src/tests/lib/libc/locale/
t_io.c 141 struct ibuf *ib = vp; local in function:readfn
142 size_t todo = MIN((size_t)len, ib->buflen - ib->off);
144 memcpy(buf, ib->buf + ib->off, todo);
145 ib->off += todo;
158 struct ibuf ib = { local in function:ATF_TC_BODY
162 FILE *fp = funopen(&ib, readfn, NULL, NULL, NULL);
186 struct ibuf ib = { local in function:ATF_TC_BODY
190 FILE *fp = funopen(&ib, readfn, NULL, NULL, NULL)
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  /src/usr.sbin/iteconfig/
iteconfig.c 82 struct itebell ib, newib; local in function:main
92 fd = initialize(_PATH_CONSOLE, &is, &ib, &newis, &newib);
107 fd = initialize(optarg, &is, &ib, &newis, &newib);
154 if (memcmp(&newib, &ib, sizeof(ib))) {
156 xioctl(fd, ITEIOCGBELL, &ib);
186 ib.volume, ib.msec, ib.pitch);
257 initialize(file, is, ib, newis, newib
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