| /src/sys/arch/amiga/amiga/ |
| cia.c | 111 dispatch_cia_ints (0, ciaa.icr);
123 dispatch_cia_ints (1, ciab.icr);
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| cia.h | 51 volatile unsigned char icr; char padd[0xff]; member in struct:CIA
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| amiga_init.c | 864 ciaa.icr = 0x7f; /* and keyboard */
865 ciab.icr = 0x7f; /* and again */
889 ciaa.icr = 0x7f; /* and keyboard */
890 ciab.icr = 0x7f; /* and again */
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| /src/sys/arch/amiga/dev/ |
| clock.c | 178 clockcia->icr = 1 << 0; /* disable timer A interrupt */
179 interval = clockcia->icr; /* and make sure it's clear */
218 clockcia->icr = (1<<7) | (1<<0);
277 * should read ICR and if there's an int pending, adjust
278 * interval. However, since reading ICR clears the interrupt,
620 clockcia->icr = (1<<7) | (1<<1);
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| kbd.c | 300 ciaa.icr = CIA_ICR_SP; /* CIA SP interrupt disable */
308 ciaa.icr = CIA_ICR_IR_SC | CIA_ICR_SP;
317 ciaa.icr = CIA_ICR_IR_SC | CIA_ICR_SP; /* SP interrupt enable */
656 for (ints = 0; ! ((mask = ciaa.icr) & CIA_ICR_SP);
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| par.c | 194 ciaa.icr = CIA_ICR_IR_SC | CIA_ICR_FLG;
211 ciaa.icr = CIA_ICR_FLG;
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| fd.c | 466 ciab.icr = CIA_ICR_FLG;
653 ciab.icr = CIA_ICR_FLG;
1403 ciab.icr = CIA_ICR_IR_SC | CIA_ICR_FLG;
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| /src/sys/dev/pci/ |
| if_ath_pci.c | 257 pcireg_t bhlc, csr, icr, lattimer; local in function:ath_pci_setup
302 icr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_INTERRUPT_REG);
303 lattimer = MAX(0x10, MIN(0xf8, 8 * PCI_MIN_GNT(icr)));
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| pcireg.h | 1312 #define PCI_MAX_LAT(icr) \
1313 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
1317 #define PCI_MIN_GNT(icr) \
1318 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
1322 #define PCI_INTERRUPT_GRANT(icr) \
1323 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
1327 #define PCI_INTERRUPT_LATENCY(icr) \
1328 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
1332 #define PCI_INTERRUPT_PIN(icr) \
1333 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK
[all...] |
| if_dge.c | 1521 uint32_t icr; local in function:dge_intr
1525 icr = CSR_READ(sc, DGE_ICR);
1526 if ((icr & sc->sc_icr) == 0)
1529 rnd_add_uint32(&sc->rnd_source, icr);
1534 if (icr & (ICR_RXDMT0 | ICR_RXT0)) {
1538 icr & (ICR_RXDMT0 | ICR_RXT0)));
1545 if (icr & ICR_TXDW) {
1551 if (icr & ICR_TXQE)
1556 if (icr & (ICR_LSC | ICR_RXSEQ)) {
1558 dge_linkintr(sc, icr);
[all...] |
| pciconf.c | 593 pcireg_t classreg, cmd, icr, bhlc, bar, mask, bar64, mask64, local in function:pci_do_device_query
661 icr = pci_conf_read(pb->pc, tag, PCI_INTERRUPT_REG);
662 pd->ipin = PCI_INTERRUPT_PIN(icr);
663 pd->iline = PCI_INTERRUPT_LINE(icr);
664 pd->min_gnt = PCI_MIN_GNT(icr);
665 pd->max_lat = PCI_MAX_LAT(icr);
669 icr &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
670 icr |= (pd->iline << PCI_INTERRUPT_LINE_SHIFT);
671 pci_conf_write(pb->pc, tag, PCI_INTERRUPT_REG, icr);
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| if_ixl.c | 3413 uint32_t icr, rxintr, txintr; local in function:ixl_intr
3420 icr = ixl_rd(sc, I40E_PFINT_ICR0);
3422 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) {
3429 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) {
3435 rxintr = icr & I40E_INTR_NOTX_RX_MASK;
3436 txintr = icr & I40E_INTR_NOTX_TX_MASK;
3540 uint32_t icr, mask, reg; local in function:ixl_other_intr
3543 icr = ixl_rd(sc, I40E_PFINT_ICR0);
3546 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) {
3553 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK))
[all...] |
| if_wm.c | 10407 wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
10420 if ((icr & ICR_LSC) == 0) {
10421 if (icr & ICR_RXSEQ)
10719 wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
10728 if (icr & ICR_LSC) {
10763 } else if (icr & ICR_RXSEQ)
10775 wm_linkintr_serdes(struct wm_softc *sc, uint32_t icr)
10785 if (icr & ICR_LSC) {
10851 wm_linkintr(struct wm_softc *sc, uint32_t icr)
10857 wm_linkintr_gmii(sc, icr);
10909 uint32_t icr, rndval = 0; local in function:wm_intr_legacy
[all...] |
| if_iavf.c | 3232 uint32_t icr; local in function:iavf_intr
3239 icr = iavf_rd(sc, I40E_VFINT_ICR01);
3241 if (icr == IAVF_REG_VFR) {
3249 if (ISSET(icr, I40E_VFINT_ICR01_ADMINQ_MASK)) {
3256 if (ISSET(icr, I40E_VFINT_ICR01_QUEUE_0_MASK)) {
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| /src/sys/arch/arm/rockchip/ |
| rk_spi.c | 478 uint32_t icr = SPI_ICR_CCI; local in function:rk_spi_intr
486 icr |= SPI_ICR_CRFOI;
490 icr |= SPI_ICR_CRFUI;
494 icr |= SPI_ICR_CTFOI;
514 SPIREG_WRITE(sc, SPI_ICR, icr);
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| /src/sys/dev/qbus/ |
| if_qtreg.h | 141 short Icr;
160 #define icr qt_un0.csr0.Icr macro
193 /* define ICR definitions */
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| /src/sys/dev/ic/ |
| sunscpal.c | 254 uint16_t icr; local in function:sunscpal_dma_start
259 icr = SUNSCPAL_READ_2(sc, sunscpal_icr);
260 icr |= SUNSCPAL_ICR_DMA_ENABLE |
263 SUNSCPAL_WRITE_2(sc, sunscpal_icr, icr);
313 printf("%s: done, icr=%s\n", __func__, buffer);
324 uint16_t icr; local in function:sunscpal_dma_stop
335 icr = SUNSCPAL_READ_2(sc, sunscpal_icr);
336 icr &= ~(SUNSCPAL_ICR_DMA_ENABLE | SUNSCPAL_ICR_WORD_MODE |
338 SUNSCPAL_WRITE_2(sc, sunscpal_icr, icr);
356 if (icr & (SUNSCPAL_ICR_BUS_ERROR))
[all...] |
| sunscpalvar.h | 109 #define SUNSCPAL_BUS_PHASE(icr) ((icr) & SUNSCPAL_ICR_PHASE_MASK)
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| /src/sys/dev/cardbus/ |
| cardbus.c | 444 pcireg_t bhlc, icr, lattimer; local in function:cardbus_rescan
542 icr = cardbus_conf_read(cc, cf, tag, PCI_INTERRUPT_REG);
543 DPRINTF(("%s func%d icr 0x%08x bhlc 0x%08x -> ",
544 device_xname(sc->sc_dev), function, icr, bhlc));
565 MIN(sc->sc_max_lattimer, MAX(0x10, 8 * PCI_MIN_GNT(icr)));
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| /src/sys/arch/arm/sunxi/ |
| sun8i_crypto.c | 494 * be from us because we've kept ICR set to 0 to mask all
888 uint32_t icr; local in function:sun8i_crypto_submit
930 icr = sun8i_crypto_read(sc, SUN8I_CRYPTO_ICR);
931 icr |= __SHIFTIN(SUN8I_CRYPTO_ICR_INTR_EN_CHAN(i),
933 sun8i_crypto_write(sc, SUN8I_CRYPTO_ICR, icr);
1200 uint32_t icr; local in function:sun8i_crypto_chan_done
1216 icr = sun8i_crypto_read(sc, SUN8I_CRYPTO_ICR);
1217 icr &= ~__SHIFTIN(SUN8I_CRYPTO_ICR_INTR_EN_CHAN(i),
1219 sun8i_crypto_write(sc, SUN8I_CRYPTO_ICR, icr);
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| /src/sys/arch/hppa/dev/ |
| dino.c | 73 uint32_t icr; /* 0x024 rw intr control reg */ member in struct:dino_regs
1785 r->icr = 0;
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