1 /* $NetBSD: if_qtreg.h,v 1.6 2021/12/20 17:12:41 rhialto Exp $ */ 2 /* 3 * Copyright (c) 1992 Steven M. Schultz 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * @(#)if_qtreg.h 1.0 (GTE) 10/12/92 29 */ 30 /* 31 * Modification History 32 * 26 Feb 93 -- sms 33 * Add defines for number of receive and transmit ring descriptors. 34 * 35 * 12 Oct 92 -- Steven M. Schultz (sms) 36 * Created from the DELQA-PLUS Addendum to the DELQA User's Guide. 37 */ 38 39 #define QT_MAX_RCV 32 40 #define QT_MAX_XMT 12 41 42 /* Receive ring descriptor and bit/field definitions */ 43 44 struct qt_rring 45 { 46 short rmd0; 47 short rmd1; 48 short rmd2; 49 short rmd3; 50 short rmd4; 51 short rmd5; 52 #ifdef pdp11 53 struct qt_uba *rhost0; 54 short rhost1; 55 #else 56 short pad1, pad2; 57 #endif 58 }; 59 60 #define RMD0_ERR3 0x4000 /* Error summary. FRA|CRC|OFL|BUF */ 61 #define RMD0_FRA 0x2000 /* Framing error */ 62 #define RMD0_OFL 0x1000 /* Overflow error. Oversized packet */ 63 #define RMD0_CRC 0x0800 /* CRC error */ 64 #define RMD0_BUF 0x0400 /* Internal device buffer error */ 65 #define RMD0_STP 0x0200 /* Start of packet */ 66 #define RMD0_ENP 0x0100 /* End of packet */ 67 68 #define RMD1_MCNT 0x0fff /* Message byte count */ 69 70 #define RMD2_ERR4 0x8000 /* Error summary. BBL|CER|MIS */ 71 #define RMD2_BBL 0x4000 /* Babble error on transmit */ 72 #define RMD2_CER 0x2000 /* Collision error on transmit */ 73 #define RMD2_MIS 0x1000 /* Packet lost on receive */ 74 #define RMD2_EOR 0x0800 /* End of receive ring */ 75 #define RMD2_RON 0x0020 /* Receiver on */ 76 #define RMD2_TON 0x0010 /* Transmitter on */ 77 78 #define RMD3_OWN 0x8000 /* Ownership field. */ 79 80 #define RMD4_LADR 0xfff8 /* Octabyte aligned low address bits */ 81 82 #define RMD5_HADR 0x003f /* High 6 bits of buffer address */ 83 84 #define RMD0_BITS "\010\016FRA\015OFL\014CRC\013BUF\012STP\011ENP" 85 #define RMD2_BITS "\010\017BBL\014CER\013MIS\012EOR\06RON\05TON" 86 87 /* Transmit ring descriptor and bit/field definitions */ 88 89 struct qt_tring 90 { 91 short tmd0; 92 short tmd1; 93 short tmd2; 94 short tmd3; 95 short tmd4; 96 short tmd5; 97 #ifdef pdp11 98 struct qt_uba *thost0; 99 short thost1; 100 #else 101 short pad1, pad2; 102 #endif 103 }; 104 105 #define TMD0_ERR1 0x4000 /* Error summary. LCO|LCA|RTR */ 106 #define TMD0_MOR 0x1000 /* More than one retry on transmit */ 107 #define TMD0_ONE 0x0800 /* One retry on transmit */ 108 #define TMD0_DEF 0x0400 /* Deferral during transmit */ 109 110 #define TMD1_LCO 0x1000 /* Late collision on transmit */ 111 #define TMD1_LCA 0x0800 /* Loss of carrier on transmit */ 112 #define TMD1_RTR 0x0400 /* Retry error on transmit */ 113 #define TMD1_TDR 0x03ff /* Time Domain Reflectometry value */ 114 115 #define TMD2_ERR2 0x8000 /* Error summary. BBL|CER|MIS */ 116 #define TMD2_BBL 0x4000 /* Babble error on transmit */ 117 #define TMD2_CER 0x2000 /* Collision error on transmit */ 118 #define TMD2_MIS 0x1000 /* Packet lost on receive */ 119 #define TMD2_EOR 0x0800 /* Endof Receive ring reached */ 120 #define TMD2_RON 0x0020 /* Receiver on */ 121 #define TMD2_TON 0x0010 /* Transmitter on */ 122 123 #define TMD3_OWN 0x8000 /* Ownership field */ 124 #define TMD3_FOT 0x4000 /* First of two flag */ 125 #define TMD3_BCT 0x0fff /* Byte count */ 126 127 #define TMD4_LADR 0xfff8 /* Octabyte aligned low address bits */ 128 129 #define TMD5_HADR 0x003f /* High 6 bits of buffer address */ 130 131 #define TMD1_BITS "\010\015LCO\014LCA\013RTR" 132 #define TMD2_BITS "\010\017BBL\016CER\015MIS\014EOR\06RON\05TON" 133 134 /* DELQA-YM CSR layout */ 135 136 #ifdef notdef 137 struct qtcsr0 138 { 139 short Ibal; 140 short Ibah; 141 short Icr; 142 short pad0; 143 short Srqr; 144 short pad1; 145 }; 146 147 struct qtdevice 148 { 149 union { 150 u_char Sarom[12]; 151 struct qtcsr0 csr0; 152 } qt_un0; 153 short srr; 154 short arqr; 155 }; 156 157 #define ibal qt_un0.csr0.Ibal 158 #define ibah qt_un0.csr0.Ibah 159 #define srqr qt_un0.csr0.Srqr 160 #define icr qt_un0.csr0.Icr 161 #define sarom qt_un0.Sarom 162 #endif 163 164 #define CSR_IBAL 0 165 #define CSR_IBAH 2 166 #define CSR_ICR 4 167 #define CSR_SRQR 8 168 #define CSR_SRR 12 169 #define CSR_ARQR 14 170 171 172 /* SRR definitions */ 173 174 #define SRR_FES 0x8000 175 #define SRR_CHN 0x4000 176 #define SRR_NXM 0x1000 177 #define SRR_PER 0x0800 178 #define SRR_IME 0x0400 179 #define SRR_TBL 0x0200 180 #define SRR_RESP 0x0003 181 #define SRR_BITS "\010\017CHN\015NXM\014PER\013IME\012TBL" 182 183 /* SRQR definitions */ 184 185 #define SRQR_REQ 0x0003 186 187 /* ARQR definitions */ 188 189 #define ARQR_TRQ 0x8000 190 #define ARQR_RRQ 0x0080 191 #define ARQR_SR 0x0002 192 193 /* define ICR definitions */ 194 195 #define ICR_CMD 0x0001 196 197 /* DELQA registers used to shift into -T mode */ 198 199 #ifdef notdef 200 #define xcr0 qt_un0.csr0.Ibal 201 #define xcr1 qt_un0.csr0.Ibah 202 #endif 203 #define CSR_XCR0 CSR_IBAL 204 #define CSR_XCR1 CSR_IBAH 205 206 /* INIT block structure and definitions */ 207 208 struct qt_init 209 { 210 int16_t mode; 211 u_char paddr[6]; /* 48 bit physical address */ 212 uint16_t laddr[4]; /* 64 bit logical address filter */ 213 uint16_t rx_lo; /* low 16 bits of receive ring addr */ 214 uint16_t rx_hi; /* high 6 bits of receive ring addr */ 215 uint16_t tx_lo; /* low 16 bits of transmit ring addr */ 216 uint16_t tx_hi; /* high 6 bits of transmit ring addr */ 217 uint16_t options; 218 uint16_t vector; 219 uint16_t hit; 220 char passwd[6]; 221 char pad[4]; /* even on 40 byte for alignment */ 222 }; 223 224 #define INIT_MODE_PRO 0x8000 /* Promiscuous mode */ 225 #define INIT_MODE_INT 0x0040 /* Internal Loopback */ 226 #define INIT_MODE_DRT 0x0020 /* Disable Retry */ 227 #define INIT_MODE_DTC 0x0008 /* Disable Transmit CRC */ 228 #define INIT_MODE_LOP 0x0004 /* Loopback */ 229 230 #define INIT_OPTIONS_HIT 0x0002 /* Host Inactivity Timeout Flag */ 231 #define INIT_OPTIONS_INT 0x0001 /* Interrupt Enable Flag */ 232
Indexes created Sat Sep 20 22:09:52 GMT 2025