| /src/sys/arch/bebox/stand/boot/ |
| ns16550.h | 50 #define iir fcr macro
|
| /src/sys/arch/prep/stand/boot/ |
| ns16550.h | 49 #define iir fcr macro
|
| /src/sys/arch/rs6000/stand/boot/ |
| ns16550.h | 49 #define iir fcr macro
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_gt_irq.c | 21 static void guc_irq_handler(struct intel_guc *guc, u16 iir)
23 if (iir & GUC_INTR_GUC2HOST)
28 cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
32 if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
35 if (iir & GT_RENDER_USER_INTERRUPT) {
79 const u16 iir)
82 return guc_irq_handler(>->uc.guc, iir);
85 return gen11_rps_irq_handler(>->rps, iir);
87 WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
88 instance, iir);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_irq.c | 178 i915_reg_t iir, i915_reg_t ier)
185 /* IIR can theoretically queue up two events. Be paranoid. */
186 intel_uncore_write(uncore, iir, 0xffffffff);
187 intel_uncore_posting_read(uncore, iir);
188 intel_uncore_write(uncore, iir, 0xffffffff);
189 intel_uncore_posting_read(uncore, iir);
199 /* IIR can theoretically queue up two events. Be paranoid. */
242 i915_reg_t iir)
244 gen3_assert_iir_is_zero(uncore, iir);
1301 u32 iir, u32 pipe_stats[I915_MAX_PIPES]
1537 u32 iir, gt_iir, pm_iir; local in function:valleyview_irq_handler
1622 u32 master_ctl, iir; local in function:cherryview_irq_handler
2255 u32 iir; local in function:gen8_de_irq_handler
2436 u32 iir; local in function:gen11_gu_misc_irq_ack
3619 u16 iir; local in function:i8xx_irq_handler
3720 u32 iir; local in function:i915_irq_handler
3863 u32 iir; local in function:i965_irq_handler
[all...] |
| i915_irq.h | 127 i915_reg_t iir, i915_reg_t ier);
134 i915_reg_t iir);
144 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
162 type##IIR)
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_irq.c | 39 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
187 u32 iir; local in function:i915_driver_irq_handler
192 iir = I915_READ(IIR);
193 if (!iir)
199 * Clear the PIPE(A|B)STAT regs before the IIR
201 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
208 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
215 I915_WRITE(IIR, iir);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| interrupt.c | 47 #define iir_to_regbase(iir) (iir - 0x8)
275 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
281 * This function is used to emulate the generic IIR register behavior.
292 u32 iir = *(u32 *)p_data; local in function:intel_vgpu_reg_iir_handler
294 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
295 (vgpu_vreg(vgpu, reg) ^ iir));
300 vgpu_vreg(vgpu, reg) &= ~iir;
367 u32 iir = regbase_to_iir local in function:update_upstream_irq
[all...] |
| /src/sys/arch/sandpoint/sandpoint/ |
| satmgr.c | 185 #define IIR 2
643 int iir; local in function:hwintr
646 iir = CSR_READ(sc, IIR) & IIR_IMASK;
647 if (iir == IIR_NOPEND) {
652 switch (iir) {
664 iir = CSR_READ(sc, IIR) & IIR_IMASK;
665 } while (iir != IIR_NOPEND);
|
| /src/sys/dev/ic/ |
| com.c | 739 * IIR changes into the EFR if LCR is set to LCR_EERS
740 * on 16650s. We also know IIR != 0 at this point.
2374 u_char lsr, iir; local in function:comintr
2382 iir = CSR_READ_1(regsp, COM_REG_IIR);
2386 (iir & IIR_BUSY) == IIR_BUSY) {
2398 iir = CSR_READ_1(regsp, COM_REG_IIR);
2403 (iir & IIR_BUSY) == IIR_BUSY) {
2440 if (ISSET(iir, IIR_NOPEND)) {
2466 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY))
2532 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY)
[all...] |
| /src/sys/arch/hp300/dev/ |
| dnkbd.c | 879 uint8_t iir, lsr, c; local in function:dnkbd_intr
886 iir = bus_space_read_1(bst, bsh, com_iir);
888 switch (iir & IIR_IMASK) {
940 if (iir & IIR_NOPEND)
|
| /src/sys/arch/hppa/hppa/ |
| trap.S | 314 stw %r0, TF_CR19-TRAPFRAME_SIZEOF(%sr1, %t3) /* iir */
874 mfctl %iir, %arg0
1351 mfctl %iir, %r16
1472 mfctl %iir, %r16
1653 mfctl %iir, %r16
1994 mfctl %iir, %t2
2211 mfctl %iir, %r8
|
| /src/sys/arch/arm/s3c2xx0/ |
| sscom.c | 1741 rnd_add_uint32(&sc->rnd_source, iir | rsr);
1806 rnd_add_uint32(&sc->rnd_source, iir | rsr);
|
| /src/sys/arch/arm/ixp12x0/ |
| ixp12x0_com.c | 1179 rnd_add_uint32(&sc->rnd_source, iir | lsr);
|
| /src/sys/arch/sh3/dev/ |
| scif.c | 1405 rnd_add_uint32(&sc->rnd_source, iir | lsr);
|
| sci.c | 1265 rnd_add_uint32(&sc->rnd_source, iir | lsr);
|
| /src/sys/arch/arm/sa11x0/ |
| sa11x0_com.c | 1405 rnd_add_uint32(&sc->rnd_source, iir | lsr);
|
| /src/sys/arch/arm/imx/ |
| imxuart.c | 1795 rnd_add_uint32(&sc->rnd_source, iir | lsr);
|
| /src/sys/arch/arm/xilinx/ |
| zynq_uart.c | 1680 rnd_add_uint32(&sc->rnd_source, iir | lsr);
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 221 iir: .equ 19 ; Interruption Instruction Register label
|
