| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| thumbemu.c | 272 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
280 * ainstr |= (imm5 << 7);
411 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
436 * ainstr |= (imm5 << 7);
449 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
458 * ainstr |= (imm5 << 7);
471 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
486 // LSL{S}<c>.W <Rd>,<Rm>,#<imm5>
516 * ainstr |= (imm5 << 7);
527 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7) local
551 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
586 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
624 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
651 ARMword imm5 = (ntBITS (12, 14) << 2) | ntBITS (6, 7); local
1866 ARMword imm5 = tBIT (9) << 5 | tBITS (3, 7); local
[all...] |
| /src/external/gpl3/binutils/dist/include/opcode/ |
| cr16.h | 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon10627
|
| nds32.h | 116 #define N16_TYPE5(op10, imm5) \
117 (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
124 #define N16_TYPE25(op8, re, imm5) \
126 | __MF (imm5, 0, 5))
|
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| cr16.h | 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon12091
|
| nds32.h | 116 #define N16_TYPE5(op10, imm5) \
117 (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
124 #define N16_TYPE25(op8, re, imm5) \
126 | __MF (imm5, 0, 5))
|
| /src/external/gpl3/gdb/dist/sim/v850/ |
| simops.c | 611 /* add sign_extend(imm5), reg */
745 /* mulh sign_extend(imm5), reg2 */
799 /* cmp sign_extend(imm5), reg */
890 /* satadd sign_extend(imm5), reg */
1114 /* mov sign_extend(imm5), reg */
1142 /* sar zero_extend(imm5),reg1 */
1195 /* shl zero_extend(imm5),reg1 */
1247 /* shr zero_extend(imm5),reg1 */
2190 /* sdivun imm5, reg1, reg2, reg3 */
2199 unsigned int imm5;
2196 unsigned int imm5; local
2231 unsigned int imm5; local
2266 unsigned int imm5; local
2301 unsigned int imm5; local
[all...] |
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| cr16.h | 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon21479
|
| nds32.h | 116 #define N16_TYPE5(op10, imm5) \
117 (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
124 #define N16_TYPE25(op8, re, imm5) \
126 | __MF (imm5, 0, 5))
|
| /src/external/gpl3/gdb.old/dist/sim/v850/ |
| simops.c | 611 /* add sign_extend(imm5), reg */
745 /* mulh sign_extend(imm5), reg2 */
799 /* cmp sign_extend(imm5), reg */
890 /* satadd sign_extend(imm5), reg */
1114 /* mov sign_extend(imm5), reg */
1142 /* sar zero_extend(imm5),reg1 */
1195 /* shl zero_extend(imm5),reg1 */
1247 /* shr zero_extend(imm5),reg1 */
2190 /* sdivun imm5, reg1, reg2, reg3 */
2199 unsigned int imm5;
2196 unsigned int imm5; local
2231 unsigned int imm5; local
2266 unsigned int imm5; local
2301 unsigned int imm5; local
[all...] |
| /src/external/gpl3/gdb/dist/include/opcode/ |
| cr16.h | 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon1067
|
| nds32.h | 116 #define N16_TYPE5(op10, imm5) \
117 (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
124 #define N16_TYPE25(op8, re, imm5) \
126 | __MF (imm5, 0, 5))
|
| /src/external/gpl3/binutils/dist/opcodes/ |
| cr16-opc.c | 148 SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr),
158 SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
558 {5, arg_ic, OP_SIGNED}, /* imm5 */
|
| arm-dis.c | 8616 long imm5;
8617 imm5 = ((given & 0x100) >> 4) | (given & 0xf);
8619 (imm5 == 0) ? 32 : imm5);
9666 unsigned int imm5 = 0;
9667 imm5 |= arm_decode_field (given, 6, 7);
9668 imm5 |= (arm_decode_field (given, 12, 14) << 2);
9670 (imm5 == 0) ? 32 : imm5);
8615 long imm5; local
9665 unsigned int imm5 = 0; local
|
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| cr16-opc.c | 148 SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr),
158 SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
558 {5, arg_ic, OP_SIGNED}, /* imm5 */
|
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| cr16-opc.c | 148 SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr),
158 SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
558 {5, arg_ic, OP_SIGNED}, /* imm5 */
|
| /src/external/gpl3/gdb/dist/opcodes/ |
| cr16-opc.c | 148 SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr),
158 SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
558 {5, arg_ic, OP_SIGNED}, /* imm5 */
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| bfin-parse.y | 213 #define imm5(x) EXPR_VALUE (x)
1965 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
2012 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
2017 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
3432 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3446 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3451 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3465 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0)
[all...] |
| bfin-parse.c | 264 #define imm5(x) EXPR_VALUE (x) macro
4388 (yyval.instr) = DSP32SHIFTIMM (3, 0, imm5 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
4442 (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
4447 (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
6159 (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-5].expr)), imm5 ((yyvsp[-1].expr)), 1, 1, 1);
6176 (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-1].expr)), 0, 1, 0, 1);
6181 (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-1].expr)), 0, 1, 1);
6198 (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-7].expr)), imm5 ((yyvsp[-3].expr)), 1, 1, 0)
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| bfin-parse.y | 213 #define imm5(x) EXPR_VALUE (x)
1965 $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
2012 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
2017 $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
3432 $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
3446 $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
3451 $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
3465 $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0)
[all...] |
| bfin-parse.c | 264 #define imm5(x) EXPR_VALUE (x) macro
4388 (yyval.instr) = DSP32SHIFTIMM (3, 0, imm5 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
4442 (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
4447 (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
6159 (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-5].expr)), imm5 ((yyvsp[-1].expr)), 1, 1, 1);
6176 (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-1].expr)), 0, 1, 0, 1);
6181 (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-1].expr)), 0, 1, 1);
6198 (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-7].expr)), imm5 ((yyvsp[-3].expr)), 1, 1, 0)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| simulator.c | 2624 unsigned imm5 = INSTR (20, 16); local
2633 if (imm5 & 0x1)
2636 index = (imm5 >> 1) & 0xF;
2638 else if (imm5 & 0x2)
2641 index = (imm5 >> 2) & 0x7;
2643 else if (full && (imm5 & 0x4))
2646 index = (imm5 >> 3) & 0x3;
2694 unsigned imm5 = INSTR (20, 16); local
2705 if (imm5 & 0x1)
2708 index = (imm5 >> 1) & 0xF
7763 uint32_t imm5 = INSTR (9, 5); local
[all...] |
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| simulator.c | 2624 unsigned imm5 = INSTR (20, 16); local
2633 if (imm5 & 0x1)
2636 index = (imm5 >> 1) & 0xF;
2638 else if (imm5 & 0x2)
2641 index = (imm5 >> 2) & 0x7;
2643 else if (full && (imm5 & 0x4))
2646 index = (imm5 >> 3) & 0x3;
2694 unsigned imm5 = INSTR (20, 16); local
2705 if (imm5 & 0x1)
2708 index = (imm5 >> 1) & 0xF
7763 uint32_t imm5 = INSTR (9, 5); local
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/cr16/ |
| interp.c | 131 case imm3: case imm4: case imm5: case imm6:
|
| /src/external/gpl3/gdb/dist/sim/cr16/ |
| interp.c | 131 case imm3: case imm4: case imm5: case imm6:
|
| /src/sys/arch/aarch64/aarch64/ |
| disasm.c | 1493 OP5FUNC(op_ccmn_imm, sf, imm5, cond, Rn, nzcv)
1497 imm5,
1511 OP5FUNC(op_ccmp_imm, sf, imm5, cond, Rn, nzcv)
1515 imm5,
|
