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    Searched refs:input_port (Results 1 - 25 of 46) sorted by relevancy

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  /src/external/gpl3/gdb.old/dist/sim/bfin/
dv-bfin_dmac.c 97 { "ppi@0", 0, 0, input_port, },
98 { "rsi", 1, 0, input_port, },
99 { "sport@0_rx", 2, 0, input_port, },
100 { "sport@0_tx", 3, 0, input_port, },
101 { "sport@1_tx", 4, 0, input_port, },
102 { "sport@1_rx", 5, 0, input_port, },
103 { "spi@0", 6, 0, input_port, },
104 { "spi@1", 7, 0, input_port, },
105 { "uart2@0_rx", 8, 0, input_port, },
106 { "uart2@0_tx", 9, 0, input_port, },
    [all...]
dv-bfin_pint.c 181 { "piq0@"#n, ENC(n, 0), 0, input_port, }, \
182 { "piq1@"#n, ENC(n, 1), 0, input_port, }, \
183 { "piq2@"#n, ENC(n, 2), 0, input_port, }, \
184 { "piq3@"#n, ENC(n, 3), 0, input_port, }, \
185 { "piq4@"#n, ENC(n, 4), 0, input_port, }, \
186 { "piq5@"#n, ENC(n, 5), 0, input_port, }, \
187 { "piq6@"#n, ENC(n, 6), 0, input_port, }, \
188 { "piq7@"#n, ENC(n, 7), 0, input_port, }, \
189 { "piq8@"#n, ENC(n, 8), 0, input_port, }, \
190 { "piq9@"#n, ENC(n, 9), 0, input_port, }, \
    [all...]
dv-bfin_sic.c 601 { "int0@"#n, ENC(n, 0), 0, input_port, }, \
602 { "int1@"#n, ENC(n, 1), 0, input_port, }, \
603 { "int2@"#n, ENC(n, 2), 0, input_port, }, \
604 { "int3@"#n, ENC(n, 3), 0, input_port, }, \
605 { "int4@"#n, ENC(n, 4), 0, input_port, }, \
606 { "int5@"#n, ENC(n, 5), 0, input_port, }, \
607 { "int6@"#n, ENC(n, 6), 0, input_port, }, \
608 { "int7@"#n, ENC(n, 7), 0, input_port, }, \
609 { "int8@"#n, ENC(n, 8), 0, input_port, }, \
610 { "int9@"#n, ENC(n, 9), 0, input_port, }, \
    [all...]
dv-bfin_cec.c 145 { "emu", IVG_EMU, 0, input_port, },
146 { "rst", IVG_RST, 0, input_port, },
147 { "nmi", IVG_NMI, 0, input_port, },
148 { "evx", IVG_EVX, 0, input_port, },
149 { "ivhw", IVG_IVHW, 0, input_port, },
150 { "ivtmr", IVG_IVTMR, 0, input_port, },
151 { "ivg7", IVG7, 0, input_port, },
152 { "ivg8", IVG8, 0, input_port, },
153 { "ivg9", IVG9, 0, input_port, },
154 { "ivg10", IVG10, 0, input_port, },
    [all...]
  /src/external/gpl3/gdb/dist/sim/bfin/
dv-bfin_dmac.c 97 { "ppi@0", 0, 0, input_port, },
98 { "rsi", 1, 0, input_port, },
99 { "sport@0_rx", 2, 0, input_port, },
100 { "sport@0_tx", 3, 0, input_port, },
101 { "sport@1_tx", 4, 0, input_port, },
102 { "sport@1_rx", 5, 0, input_port, },
103 { "spi@0", 6, 0, input_port, },
104 { "spi@1", 7, 0, input_port, },
105 { "uart2@0_rx", 8, 0, input_port, },
106 { "uart2@0_tx", 9, 0, input_port, },
    [all...]
dv-bfin_pint.c 181 { "piq0@"#n, ENC(n, 0), 0, input_port, }, \
182 { "piq1@"#n, ENC(n, 1), 0, input_port, }, \
183 { "piq2@"#n, ENC(n, 2), 0, input_port, }, \
184 { "piq3@"#n, ENC(n, 3), 0, input_port, }, \
185 { "piq4@"#n, ENC(n, 4), 0, input_port, }, \
186 { "piq5@"#n, ENC(n, 5), 0, input_port, }, \
187 { "piq6@"#n, ENC(n, 6), 0, input_port, }, \
188 { "piq7@"#n, ENC(n, 7), 0, input_port, }, \
189 { "piq8@"#n, ENC(n, 8), 0, input_port, }, \
190 { "piq9@"#n, ENC(n, 9), 0, input_port, }, \
    [all...]
dv-bfin_sic.c 601 { "int0@"#n, ENC(n, 0), 0, input_port, }, \
602 { "int1@"#n, ENC(n, 1), 0, input_port, }, \
603 { "int2@"#n, ENC(n, 2), 0, input_port, }, \
604 { "int3@"#n, ENC(n, 3), 0, input_port, }, \
605 { "int4@"#n, ENC(n, 4), 0, input_port, }, \
606 { "int5@"#n, ENC(n, 5), 0, input_port, }, \
607 { "int6@"#n, ENC(n, 6), 0, input_port, }, \
608 { "int7@"#n, ENC(n, 7), 0, input_port, }, \
609 { "int8@"#n, ENC(n, 8), 0, input_port, }, \
610 { "int9@"#n, ENC(n, 9), 0, input_port, }, \
    [all...]
dv-bfin_cec.c 145 { "emu", IVG_EMU, 0, input_port, },
146 { "rst", IVG_RST, 0, input_port, },
147 { "nmi", IVG_NMI, 0, input_port, },
148 { "evx", IVG_EVX, 0, input_port, },
149 { "ivhw", IVG_IVHW, 0, input_port, },
150 { "ivtmr", IVG_IVTMR, 0, input_port, },
151 { "ivg7", IVG7, 0, input_port, },
152 { "ivg8", IVG8, 0, input_port, },
153 { "ivg9", IVG9, 0, input_port, },
154 { "ivg10", IVG10, 0, input_port, },
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/lm32/
dv-lm32cpu.c 76 {"int0", INT0_PORT, 0, input_port,},
77 {"int1", INT1_PORT, 0, input_port,},
78 {"int2", INT2_PORT, 0, input_port,},
79 {"int3", INT3_PORT, 0, input_port,},
80 {"int4", INT4_PORT, 0, input_port,},
81 {"int5", INT5_PORT, 0, input_port,},
82 {"int6", INT6_PORT, 0, input_port,},
83 {"int7", INT7_PORT, 0, input_port,},
84 {"int8", INT8_PORT, 0, input_port,},
85 {"int9", INT9_PORT, 0, input_port,},
    [all...]
  /src/external/gpl3/gdb/dist/sim/lm32/
dv-lm32cpu.c 76 {"int0", INT0_PORT, 0, input_port,},
77 {"int1", INT1_PORT, 0, input_port,},
78 {"int2", INT2_PORT, 0, input_port,},
79 {"int3", INT3_PORT, 0, input_port,},
80 {"int4", INT4_PORT, 0, input_port,},
81 {"int5", INT5_PORT, 0, input_port,},
82 {"int6", INT6_PORT, 0, input_port,},
83 {"int7", INT7_PORT, 0, input_port,},
84 {"int8", INT8_PORT, 0, input_port,},
85 {"int9", INT9_PORT, 0, input_port,},
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/mips/
dv-tx3904irc.c 144 { "int1", INT1_PORT, 0, input_port, },
145 { "int2", INT2_PORT, 0, input_port, },
146 { "int3", INT3_PORT, 0, input_port, },
147 { "int4", INT4_PORT, 0, input_port, },
148 { "int5", INT5_PORT, 0, input_port, },
149 { "int6", INT6_PORT, 0, input_port, },
150 { "int7", INT7_PORT, 0, input_port, },
152 { "dmac3", DMAC3_PORT, 0, input_port, },
153 { "dmac2", DMAC2_PORT, 0, input_port, },
154 { "dmac1", DMAC1_PORT, 0, input_port, },
    [all...]
dv-tx3904cpu.c 103 { "reset", RESET_PORT, 0, input_port, },
104 { "nmi", NMI_PORT, 0, input_port, },
105 { "level", LEVEL_PORT, 0, input_port, },
  /src/external/gpl3/gdb/dist/sim/mips/
dv-tx3904irc.c 144 { "int1", INT1_PORT, 0, input_port, },
145 { "int2", INT2_PORT, 0, input_port, },
146 { "int3", INT3_PORT, 0, input_port, },
147 { "int4", INT4_PORT, 0, input_port, },
148 { "int5", INT5_PORT, 0, input_port, },
149 { "int6", INT6_PORT, 0, input_port, },
150 { "int7", INT7_PORT, 0, input_port, },
152 { "dmac3", DMAC3_PORT, 0, input_port, },
153 { "dmac2", DMAC2_PORT, 0, input_port, },
154 { "dmac1", DMAC1_PORT, 0, input_port, },
    [all...]
dv-tx3904cpu.c 103 { "reset", RESET_PORT, 0, input_port, },
104 { "nmi", NMI_PORT, 0, input_port, },
105 { "level", LEVEL_PORT, 0, input_port, },
  /src/external/gpl3/gdb.old/dist/sim/mn10300/
dv-mn103int.c 224 { "ack", ACK_PORT, 0, input_port, },
228 { "nmirq", G0_PORT + 0, 0, input_port, },
229 { "watchdog", G0_PORT + 1, 0, input_port, },
230 { "syserr", G0_PORT + 2, 0, input_port, },
232 { "timer-0-underflow", G2_PORT, 0, input_port, },
233 { "timer-1-underflow", G3_PORT, 0, input_port, },
234 { "timer-2-underflow", G4_PORT, 0, input_port, },
235 { "timer-3-underflow", G5_PORT, 0, input_port, },
236 { "timer-4-underflow", G6_PORT, 0, input_port, },
237 { "timer-5-underflow", G7_PORT, 0, input_port, },
    [all...]
dv-mn103cpu.c 145 { "reset", RESET_PORT, 0, input_port, },
146 { "nmi", NMI_PORT, 0, input_port, },
147 { "level", LEVEL_PORT, 0, input_port, },
  /src/external/gpl3/gdb/dist/sim/mn10300/
dv-mn103int.c 224 { "ack", ACK_PORT, 0, input_port, },
228 { "nmirq", G0_PORT + 0, 0, input_port, },
229 { "watchdog", G0_PORT + 1, 0, input_port, },
230 { "syserr", G0_PORT + 2, 0, input_port, },
232 { "timer-0-underflow", G2_PORT, 0, input_port, },
233 { "timer-1-underflow", G3_PORT, 0, input_port, },
234 { "timer-2-underflow", G4_PORT, 0, input_port, },
235 { "timer-3-underflow", G5_PORT, 0, input_port, },
236 { "timer-4-underflow", G6_PORT, 0, input_port, },
237 { "timer-5-underflow", G7_PORT, 0, input_port, },
    [all...]
dv-mn103cpu.c 145 { "reset", RESET_PORT, 0, input_port, },
146 { "nmi", NMI_PORT, 0, input_port, },
147 { "level", LEVEL_PORT, 0, input_port, },
  /src/external/gpl3/gdb/dist/sim/ppc/
basics.h 66 input_port, enumerator in enum:__anon19872
  /src/external/gpl3/gdb.old/dist/sim/ppc/
basics.h 66 input_port, enumerator in enum:__anon22611
  /src/external/gpl3/gdb.old/dist/sim/common/
sim-basics.h 106 input_port, enumerator in enum:__anon21942
  /src/external/gpl3/gdb/dist/sim/common/
sim-basics.h 106 input_port, enumerator in enum:__anon1427
  /src/external/gpl3/gdb.old/dist/sim/m68hc11/
dv-m68hc11.c 179 { "reset", RESET_PORT, 0, input_port, },
180 { "nmi", NMI_PORT, 0, input_port, },
181 { "irq", IRQ_PORT, 0, input_port, },
183 { "set-port-a", SET_PORT_A, 0, input_port, },
184 { "set-port-c", SET_PORT_C, 0, input_port, },
185 { "set-port-d", SET_PORT_D, 0, input_port, },
187 { "cpu-write-port", CPU_WRITE_PORT, 0, input_port, },
  /src/external/gpl3/gdb/dist/sim/m68hc11/
dv-m68hc11.c 179 { "reset", RESET_PORT, 0, input_port, },
180 { "nmi", NMI_PORT, 0, input_port, },
181 { "irq", IRQ_PORT, 0, input_port, },
183 { "set-port-a", SET_PORT_A, 0, input_port, },
184 { "set-port-c", SET_PORT_C, 0, input_port, },
185 { "set-port-d", SET_PORT_D, 0, input_port, },
187 { "cpu-write-port", CPU_WRITE_PORT, 0, input_port, },
  /src/external/gpl3/gdb.old/dist/sim/cris/
dv-cris.c 85 { "int", INT_PORT, 0, input_port },

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