| /src/sys/arch/sgimips/include/ |
| sysconf.h | 67 * intr0-intr5 - CPU interrupt handler
83 void (*intr5)(vaddr_t, uint32_t, uint32_t); member in struct:platform
|
| /src/sys/arch/sgimips/sgimips/ |
| cpu.c | 123 (void)(*platform.intr5)(pc, status, pending);
|
| machdep.c | 218 .intr5 = unimpl_intr
582 platform.intr5 = mips3_clock_intr;
586 platform.intr5 = mips3_clock_intr;
590 platform.intr5 = mips3_clock_intr;
594 platform.intr5 = mips3_clock_intr;
|
| /src/sys/arch/sgimips/dev/ |
| ctl.c | 107 platform.intr5 = ctl_bus_error;
|
| pic.c | 180 platform.intr5 = pic_bus_error;
|
| /src/sys/dev/ic/ |
| arn5008.c | 1224 uint32_t intr, intr5, sync; local
1264 intr5 = AR_READ(sc, AR_ISR_S5_S);
1266 if (intr5 & AR_ISR_GENTMR) {
1269 MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
1270 MS(intr5, AR_ISR_S5_GENTIMER_THRESH));
1274 if (intr5 & AR_ISR_S5_TIM_TIMER) {
|
| arn9003.c | 1427 uint32_t intr5 = AR_READ(sc, AR_ISR_S5_S); local
1431 MS(intr5, AR_ISR_S5_GENTIMER_TRIG),
1432 MS(intr5, AR_ISR_S5_GENTIMER_THRESH));
1434 __USE(intr5);
|
