Searched refs:irqmask (Results 1 - 8 of 8) sorted by relevance

/src/sys/arch/mips/adm5120/
H A Dadm5120_intr.c188 uint32_t irqmask; local in function:adm5120_intr_establish
215 irqmask = 1 << irq;
220 REG_READ(ICU_MODE_REG) | irqmask);
223 REG_READ(ICU_MODE_REG) & ~irqmask);
226 REG_WRITE(ICU_ENABLE_REG, irqmask);
238 uint32_t irqmask; local in function:adm5120_intr_disestablish
254 irqmask = 1 << irq; /* only used as a mask from here on */
257 REG_WRITE(ICU_DISABLE_REG, irqmask);
268 uint32_t irqmask, irqstat; local in function:evbmips_iointr
281 irqmask
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/src/sys/arch/powerpc/ibm4xx/
H A Dpic_uic.c340 const uint32_t irqmask = IRQ_TO_MASK(irq); local in function:uic_disable_irq
341 if ((uic->uic_intr_enable & irqmask) == 0)
343 uic->uic_intr_enable ^= irqmask;
347 pic->pic_name, irq, irqmask);
355 const uint32_t irqmask = IRQ_TO_MASK(irq); local in function:uic_enable_irq
356 if ((uic->uic_intr_enable & irqmask) != 0)
358 uic->uic_intr_enable ^= irqmask;
362 pic->pic_name, irq, irqmask);
370 const uint32_t irqmask = IRQ_TO_MASK(irq); local in function:uic_ack_irq
373 uic->uic_intr_status &= ~irqmask;
387 const uint32_t irqmask = uic->uic_intr_status; local in function:uic_get_irq
389 const uint32_t irqmask = (*uic->uic_mf_intr_status)(); local in function:uic_get_irq
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/src/sys/arch/evbppc/nintendo/
H A Dpic_pi.c57 uint32_t irqmask; member in struct:pic_state
91 pic_s[cpu_num].irqmask |= __BIT(irq);
92 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
100 pic_s[cpu_num].irqmask &= ~__BIT(irq);
101 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
134 pend = raw & pic_s[cpu_num].irqmask;
141 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
152 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
174 pic_s[cpu_num].irqmask = 0;
/src/sys/dev/pcmcia/
H A Dpcmcia_cis_quirks.c67 .irqmask = 0xffff, /* irqmask */
85 .irqmask = 0xffff, /* irqmask */
120 .irqmask = 0xffff, /* irqmask */
139 .irqmask = 0xdeb8, /* irqmask */
158 .irqmask = 0xdeb8, /* irqmask */
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H A Dpcmciavar.h99 u_int16_t irqmask; member in struct:pcmcia_config_entry
H A Dpcmcia_cis.c640 printf("; irq mask %x", cfe->irqmask);
1310 cfe->irqmask =
1314 cfe->irqmask =
/src/sys/arch/mips/alchemy/
H A Dau_icu.c316 uint32_t icu_base, irqstat, irqmask; local in function:au_iointr
355 irqmask = REGVAL(icu_base + IC_MASK_READ);
360 if (mask & irqmask & irqstat) {
/src/sys/arch/arm/acpi/
H A Dacpi_pci_machdep.c494 acpi_pci_md_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irqmask) argument
498 pi->pi_unblocked |= irqmask;
502 acpi_pci_md_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irqmask) argument
506 pi->pi_unblocked &= ~irqmask;

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