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History log of /src/sys/arch/arm/acpi/acpi_pci_machdep.c
RevisionDateAuthorComments
 1.22  13-Aug-2022  jmcneill arm: acpi: Improve legacy INTx support.

For devices on a bus with no direct _PRT, use the raw intr pin with the
parent bridge's slot number to derive a pin number that can be used to
lookup the pin -> irq mapping in the parent bus's _PRT.
 1.21  21-Dec-2021  skrll Remove unneeded struct acpi_pci_intr forward declaration.
 1.20  08-Aug-2021  jmcneill Install the shared PCI INTx interrupt handler at IPL_VM to workaround a
possible interrupt storm at boot. Need to revisit this.
 1.19  07-Aug-2021  jmcneill arm: acpi: Add support for SMCCC based PCI config access.
 1.18  17-Jun-2020  thorpej <sys/extent.h> not needed here.
 1.17  15-Jun-2020  ad Use sys/cpu.h so that curcpu defined in terms of curlwp->l_cpu works too.
 1.16  13-Feb-2020  jmcneill Add support for multiple GICv3 ITS domains.
 1.15  01-Feb-2020  jmcneill Add support for NXP Layerscape PCIe Gen4 (not ECAM compliant)
 1.14  23-Jan-2020  jmcneill Add support for sharing legacy PCI interrupt sources.
 1.13  17-Jan-2020  jmcneill Add support for Arm N1 SDP PCIe host controller.

The N1 SDP has a few bugs that we need to work around:
- PCIe root port config space lives in a non-standard location.
- Access to PCIe config space of devices that do not exist results in
an sync SError. Firmware creates a "known devices" table at a fixed
physical address that we use to filter PCI conf access to only known
devices.

This change splits the Arm ACPI PCI quirks into separate files for each
host controller, and allows per-segment quirks to be applied.

These changes exposed some bugs in the MI ACPI layer related to
multi-segment support. The MI ACPI PCI code was using a shared PCI
chipset tag to access devices, and these accesses can happen before our
PCI host bridge drivers are attached! The global chipset tag is now gone,
and an MD callback can provide a custom tag on a per-segment basis.
 1.12  15-Oct-2019  jmcneill branches: 1.12.2;
Amazon Graviton maxdevs quirk no longer required as of pci.c r1.155
 1.11  14-Oct-2019  jmcneill More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.
 1.10  14-Oct-2019  jmcneill Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.
 1.9  08-Dec-2018  jmcneill branches: 1.9.4; 1.9.6;
Add support for decoding PCI ID mappings using IO remapping tables (IORT).
 1.8  16-Nov-2018  jmcneill Add intr_establish_xname support to arm and expose it to intrctl
 1.7  03-Nov-2018  jmcneill Match _PRT by segment and bus
 1.6  02-Nov-2018  jmcneill Add support for multiple PCI segments.
 1.5  31-Oct-2018  jmcneill Add MSI-X support
 1.4  21-Oct-2018  jmcneill Do not add PCI link references until the bus has been mapped
 1.3  21-Oct-2018  jmcneill Add support for PCI MSI using ARM GICv2m.
 1.2  19-Oct-2018  jmcneill branches: 1.2.2;
Add support for PCI Segment Groups.
 1.1  15-Oct-2018  jmcneill Add ARM ACPI PCI support.
 1.2.2.4  26-Dec-2018  pgoyette Sync with HEAD, resolve a few conflicts
 1.2.2.3  26-Nov-2018  pgoyette Sync with HEAD, resolve a couple of conflicts
 1.2.2.2  20-Oct-2018  pgoyette Sync with head
 1.2.2.1  19-Oct-2018  pgoyette file acpi_pci_machdep.c was added on branch pgoyette-compat on 2018-10-20 06:58:24 +0000
 1.9.6.1  15-Oct-2019  martin Pull up following revision(s) (requested by jmcneill in ticket #332):

sys/arch/arm/acpi/acpipchb.c: revision 1.10
sys/arch/arm/acpi/acpipchb.c: revision 1.11
sys/arch/arm/acpi/acpipchb.c: revision 1.12
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.3
sys/arch/arm/acpi/acpi_pci_machdep.h: revision 1.4
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.10
sys/arch/arm/acpi/acpi_pci_machdep.c: revision 1.11

Add quirks for Amazon Graviton PCIe root ports. Configuration space for the
root port is found in a child AMZN0001 resource, not the MCFG table.

-

More Amazon Graviton quirks:
- Ignore devno > 0 on the PCIe root port.
- Fixup PCIe bridge bus number register on the root port.
- Move quirk handling to acpipchb so it can be applied before the bus
is configured.

-

Fix detection of root port resources for Graviton and remove no longer required bridge fixup
 1.9.4.4  13-Apr-2020  martin Mostly merge changes from HEAD upto 20200411
 1.9.4.3  08-Apr-2020  martin Merge changes from current as of 20200406
 1.9.4.2  10-Jun-2019  christos Sync with HEAD
 1.9.4.1  08-Dec-2018  christos file acpi_pci_machdep.c was added on branch phil-wifi on 2019-06-10 22:05:50 +0000
 1.12.2.3  29-Feb-2020  ad Sync with head.
 1.12.2.2  25-Jan-2020  ad Sync with head.
 1.12.2.1  17-Jan-2020  ad Sync with head.

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