| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ti/omap/ |
| dra74x-p.dtsi | 24 /* MCAN interrupts are hard-wired to irqs 67, 68 */
26 ti,irqs-skip = <10 67 68 133 139 140>;
|
| /src/sys/arch/powerpc/pic/ |
| i8259_common.c | 69 i8259->irqs |= 1 << irq;
70 if (i8259->irqs >= 0x100) /* IRQS >= 8 in use? */
71 i8259->irqs |= 1 << IRQ_SLAVE;
73 i8259->enable_mask = ~i8259->irqs;
|
| pic_i8259.c | 73 i8259->irqs = 0;
|
| picvar.h | 40 int pic_numintrs; /* how many IRQs do we handle? */
86 uint32_t irqs; member in struct:i8259_ops
|
| /src/sys/arch/x86/x86/ |
| i8259.c | 237 int irqs, irq; local
243 irqs = 0;
246 irqs |= 1 << irq;
247 if (irqs >= 0x100) /* any IRQs >= 8 in use */
248 irqs |= 1 << IRQ_SLAVE;
249 i8259_imen = ~irqs;
|
| x86_softintr.c | 185 /* Then figure out which IRQs use each level. */
187 uint64_t irqs = 0; local
190 irqs |= 1ULL << irq;
191 ci->ci_imask[level] = irqs | unusedirqs;
|
| /src/sys/arch/macppc/macppc/ |
| pic_ohare.c | 59 uint32_t irqs[NIPL]; /* per priority level */ member in struct:ohare_ops
144 ohare->irqs[i] = 0;
204 uint32_t irqs, events, levels; local
206 irqs = in32rb(INT_STATE_REG);
207 events = irqs & ~ohare->level_mask;
211 out32rb(INT_CLEAR_REG, events | irqs);
264 evt = ohare->pending_events & ohare->irqs[lvl];
309 ohare->irqs[i] = 0;
315 ohare->irqs[level] |= (1 << i);
|
| pic_heathrow.c | 198 uint32_t irqs, events, levels; local
200 /* first the low 32 IRQs */
201 irqs = in32rb(INT_STATE_REG_L);
202 events = irqs & ~heathrow->level_mask_l;
206 out32rb(INT_CLEAR_REG_L, events | irqs);
210 irqs = in32rb(INT_STATE_REG_H);
211 events = irqs & ~heathrow->level_mask_h;
|
| /src/sys/arch/arm/ixp12x0/ |
| ixp12x0_intr.c | 69 /* Software copy of the IRQs we have enabled. */
108 ixp12x0_set_intrmask(uint32_t irqs, uint32_t pci_irqs)
110 if (irqs & (1U << IXP12X0_INTR_UART)) {
185 /* Next, figure out which IRQs are used by each IPL. */
187 int irqs = 0; local
191 irqs |= (1U << irq);
193 imask[ipl] = irqs;
228 * Now compute which IRQs must be blocked when servicing any
232 int irqs; local
236 irqs = (1U << irq)
[all...] |
| /src/sys/arch/arm/sa11x0/ |
| sa11x0_irqhandler.c | 128 /* Then figure out which IRQs use each level. */
130 int irqs = 0; local
133 irqs |= 1 << irq;
137 irqmasks[i] |= irqs;
141 irqmasks[i] &= ~irqs;
|
| /src/sys/arch/arc/isa/ |
| isabus.c | 268 /* Then figure out which IRQs use each level. */
270 int irqs = 0; local
273 irqs |= 1 << irq;
274 imask[level] = irqs;
296 int irqs = 1 << irq; local
298 irqs |= imask[q->ih_level];
299 intrmask[irq] = irqs;
302 /* Lastly, determine which IRQs are actually in use. */
304 int irqs = 0; local
307 irqs |= 1 << irq
[all...] |
| /src/sys/arch/arm/footbridge/isa/ |
| isa_machdep.c | 197 /* Then figure out which IRQs use each level. */
199 int irqs = 0; local
202 irqs |= (1U << irq);
203 imask[level] = irqs;
211 int irqs = 1 << irq; local
215 irqs |= imask[ih->ih_ipl];
216 iq->iq_mask = irqs;
219 /* Lastly, determine which IRQs are actually in use. */
221 int irqs = 0; local
224 irqs |= (1U << irq)
[all...] |
| /src/sys/arch/arm/footbridge/ |
| footbridge_irqhandler.c | 69 /* Software copy of the IRQs we have enabled. */
126 /* Next, figure out which IRQs are used by each IPL. */
128 int irqs = 0; local
131 irqs |= (1U << irq);
133 footbridge_imask[ipl] = irqs;
155 int irqs = (1U << irq); local
159 irqs |= footbridge_imask[ih->ih_ipl];
162 iq->iq_mask = irqs;
|
| /src/sys/arch/arm/xscale/ |
| becc_icu.c | 75 /* Software copy of the IRQs we have enabled. */
182 /* Next, figure out which IRQs are used by each IPL. */
184 int irqs = 0; local
187 irqs |= (1U << irq);
189 becc_imask[ipl] = irqs;
204 * Now compute which IRQs must be blocked when servicing any
208 int irqs = (1U << irq); local
214 irqs |= becc_imask[ih->ih_ipl];
215 iq->iq_mask = irqs;
282 /* Enable IRQs (don't yet use FIQs). *
[all...] |
| ixp425_intr.c | 96 /* Software copy of the IRQs we have enabled. */
207 /* Next, figure out which IRQs are used by each IPL. */
209 int irqs = 0; local
212 irqs |= (1U << irq);
214 ixp425_imask[ipl] = irqs;
243 * Now compute which IRQs must be blocked when servicing any
247 int irqs = (1U << irq); local
253 irqs |= ixp425_imask[ih->ih_ipl];
254 iq->iq_mask = irqs;
315 /* Enable IRQs (don't yet use FIQs). *
[all...] |
| /src/sys/arch/evbarm/ifpga/ |
| ifpga_intr.c | 66 /* Software copy of the IRQs we have enabled. */
158 /* Next, figure out which IRQs are used by each IPL. */
160 int irqs = 0; local
163 irqs |= (1U << irq);
165 ifpga_imask[ipl] = irqs;
180 * Now compute which IRQs must be blocked when servicing any
184 int irqs = (1U << irq); local
190 irqs |= ifpga_imask[ih->ih_ipl];
191 iq->iq_mask = irqs;
244 /* Enable IRQs (don't yet use FIQs). *
[all...] |
| /src/sys/external/bsd/drm/dist/shared-core/ |
| radeon_irq.c | 140 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS); local
147 if (irqs & R500_DISPLAY_INT_STATUS) {
165 irqs &= irq_mask;
167 if (irqs)
168 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
170 return irqs;
|
| /src/sys/arch/evbarm/iq80310/ |
| iq80310_intr.c | 74 /* Software copy of the IRQs we have enabled. */
162 /* Next, figure out which IRQs are used by each IPL. */
164 int irqs = 0; local
167 irqs |= (1U << irq);
169 iq80310_imask[ipl] = irqs;
235 * Now compute which IRQs must be blocked when servicing any
239 int irqs = (1U << irq); local
245 irqs |= iq80310_imask[ih->ih_ipl];
246 iq->iq_mask = irqs;
349 /* Enable IRQs (don't yet use FIQs). *
[all...] |
| /src/sys/arch/i386/pci/ |
| piix.c | 327 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ); local
334 irq = PIIX_PIRQ(irqs, i);
355 pcireg_t irqs = pci_conf_read(ph->ph_pc, ph->ph_tag, PIIX_CFG_PIRQ2); local
358 irq = PIIX_PIRQ(irqs, i);
|
| /src/sys/arch/arm/amlogic/ |
| meson_sdio.c | 277 const u_int irqs = SDIO_READ(sc, SDIO_IRQS_REG); local
278 if (irqs & SDIO_IRQS_CLEAR) {
279 SDIO_WRITE(sc, SDIO_IRQS_REG, irqs);
280 sc->sc_intr_irqs |= irqs;
598 const uint32_t irqs = SDIO_READ(sc, SDIO_IRQS_REG); local
599 if ((irqs & SDIO_IRQS_CMD_BUSY) == 0)
612 const uint32_t irqs = SDIO_READ(sc, SDIO_IRQS_REG); local
614 if ((irqs & SDIO_IRQS_RESPONSE_CRC7_OK) == 0) {
623 if ((irqs & crcmask) == 0) {
|
| /src/sys/arch/macppc/pci/ |
| pci_machdep.c | 161 int32_t irqs[4]; local
258 len = OF_getprop(node, "AAPL,interrupts", irqs, 4);
271 len = find_node_intr(node, &iaddr.phys_hi, irqs);
281 len = find_node_intr(node, &addr[0].phys_hi, irqs);
301 irqs[0] = 60;
308 intr |= irqs[0] & PCI_INTERRUPT_LINE_MASK;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gt/uc/ |
| intel_guc_submission.c | 564 u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; local
565 u32 dmask = irqs << 16 | irqs;
577 u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; local
578 u32 dmask = irqs << 16 | irqs;
|
| /src/sys/arch/sgimips/mace/ |
| mace.c | 313 mace_intr(int irqs)
319 if (irqs & (1 << 4)) {
329 irqs &= ~(1 << 4);
333 if ((irqs & maceintrtab[i].irq)) {
|
| /src/sys/arch/shark/isa/ |
| isa_irqhandler.c | 285 /* Then figure out which IRQs use each level. */
287 int irqs = 0; local
290 irqs |= 1 << irq;
291 irqmasks[level] = ~irqs;
|
| /src/sys/dev/ic/ |
| cpc700.c | 245 u_int32_t irqs; local
247 irqs = INL(CPC_UIC_MSR);
249 if (irqs & CPC_INTR_MASK(irq))
|
