1 /* $NetBSD: mace.c,v 1.27 2023/12/20 15:29:07 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Christopher Sekiya 5 * Copyright (c) 2002,2003 Rafal K. Boni 6 * Copyright (c) 2000 Soren S. Jorvang 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * O2 MACE 39 * 40 * The MACE is weird -- although it is a 32-bit device, writes only seem to 41 * work properly if they are 64-bit-at-once writes (at least, out in ISA 42 * space and probably MEC space -- the PCI stuff seems to be okay with _4). 43 * Therefore, the _8* routines are used even though the top 32 bits are 44 * thrown away. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.27 2023/12/20 15:29:07 thorpej Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/ioctl.h> 58 #include <sys/errno.h> 59 #include <sys/syslog.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <sys/bus.h> 64 #include <machine/cpu.h> 65 #include <machine/locore.h> 66 #include <machine/autoconf.h> 67 #include <machine/machtype.h> 68 69 #include <sgimips/mace/macevar.h> 70 #include <sgimips/mace/macereg.h> 71 #include <sgimips/dev/crimevar.h> 72 #include <sgimips/dev/crimereg.h> 73 74 #include "locators.h" 75 76 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ 77 78 struct { 79 unsigned int irq; 80 unsigned int intrmask; 81 int (*func)(void *); 82 void *arg; 83 struct evcnt evcnt; 84 char evname[32]; 85 } maceintrtab[MACE_NINTR]; 86 87 struct mace_softc { 88 device_t sc_dev; 89 90 bus_space_tag_t iot; 91 bus_space_handle_t ioh; 92 bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ 93 int nsegs; 94 bus_dma_segment_t seg; 95 bus_dmamap_t map; 96 97 void *isa_ringbuffer; 98 }; 99 100 static int mace_match(device_t, cfdata_t, void *); 101 static void mace_attach(device_t, device_t, void *); 102 static int mace_print(void *, const char *); 103 static int mace_search(device_t, cfdata_t, const int *, void *); 104 105 CFATTACH_DECL_NEW(mace, sizeof(struct mace_softc), 106 mace_match, mace_attach, NULL, NULL); 107 108 static void mace_isa_bus_mem_init(bus_space_tag_t, void *); 109 110 static struct mips_bus_space mace_isa_mbst; 111 bus_space_tag_t mace_isa_memt = NULL; 112 static int mace_isa_init = 0; 113 114 #if defined(BLINK) 115 static callout_t mace_blink_ch; 116 static void mace_blink(void *); 117 #endif 118 119 static int 120 mace_match(device_t parent, struct cfdata *match, void *aux) 121 { 122 123 /* 124 * The MACE is in the O2. 125 */ 126 if (mach_type == MACH_SGI_IP32) 127 return 1; 128 129 return 0; 130 } 131 132 void 133 mace_init_bus(void) 134 { 135 if (mace_isa_init == 1) 136 return; 137 mace_isa_init = 1; 138 mace_isa_bus_mem_init(&mace_isa_mbst, NULL); 139 mace_isa_memt = &mace_isa_mbst; 140 } 141 142 static void 143 mace_attach(device_t parent, device_t self, void *aux) 144 { 145 struct mace_softc *sc = device_private(self); 146 struct mainbus_attach_args *ma = aux; 147 uint32_t scratch; 148 149 sc->sc_dev = self; 150 #ifdef BLINK 151 callout_init(&mace_blink_ch, 0); 152 #endif 153 154 sc->iot = normal_memt; /* for mace registers */ 155 sc->dmat = &sgimips_default_bus_dma_tag; 156 157 if (bus_space_map(sc->iot, ma->ma_addr, 0, 158 BUS_SPACE_MAP_LINEAR, &sc->ioh)) 159 panic("mace_attach: could not allocate memory\n"); 160 161 aprint_normal("\n"); 162 163 aprint_debug("%s: isa sts %#"PRIx64"\n", device_xname(self), 164 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); 165 aprint_debug("%s: isa msk %#"PRIx64"\n", device_xname(self), 166 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); 167 168 mace_init_bus(); 169 170 /* 171 * Turn on most ISA interrupts. These are actually masked and 172 * registered via the CRIME, as the MACE ISA interrupt mask is 173 * really whacky and nigh on impossible to map to a sane autoconfig 174 * scheme. We do, however, turn off the count/compare timer and RTC 175 * interrupts as they are unused and conflict with the PS/2 176 * keyboard and mouse interrupts. 177 */ 178 179 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffff0aff); 180 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); 181 182 /* set up LED for solid green or blink, if that's your fancy */ 183 scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 184 scratch |= MACE_ISA_LED_RED; 185 scratch &= ~(MACE_ISA_LED_GREEN); 186 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); 187 188 #if defined(BLINK) 189 mace_blink(sc); 190 #endif 191 192 /* Initialize the maceintr elements to sane values */ 193 for (scratch = 0; scratch < MACE_NINTR; scratch++) { 194 maceintrtab[scratch].func = NULL; 195 maceintrtab[scratch].irq = 0; 196 } 197 198 config_search(self, NULL, 199 CFARGS(.search = mace_search)); 200 } 201 202 203 static int 204 mace_print(void *aux, const char *pnp) 205 { 206 struct mace_attach_args *maa = aux; 207 208 if (pnp != 0) 209 return QUIET; 210 211 if (maa->maa_offset != MACECF_OFFSET_DEFAULT) 212 aprint_normal(" offset 0x%lx", maa->maa_offset); 213 if (maa->maa_intr != MACECF_INTR_DEFAULT) 214 aprint_normal(" intr %d", maa->maa_intr); 215 if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) 216 aprint_normal(" intrmask 0x%x", maa->maa_intrmask); 217 218 return UNCONF; 219 } 220 221 static int 222 mace_search(device_t parent, struct cfdata *cf, const int *ldesc, void *aux) 223 { 224 struct mace_softc *sc = device_private(parent); 225 struct mace_attach_args maa; 226 int tryagain; 227 228 do { 229 maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; 230 maa.maa_intr = cf->cf_loc[MACECF_INTR]; 231 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; 232 maa.maa_st = normal_memt; 233 maa.maa_sh = sc->ioh; /* XXX */ 234 maa.maa_dmat = &sgimips_default_bus_dma_tag; 235 maa.isa_ringbuffer = sc->isa_ringbuffer; 236 237 tryagain = 0; 238 if (config_probe(parent, cf, &maa)) { 239 config_attach(parent, cf, &maa, mace_print, CFARGS_NONE); 240 tryagain = (cf->cf_fstate == FSTATE_STAR); 241 } 242 243 } while (tryagain); 244 245 return 0; 246 } 247 248 void * 249 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg) 250 { 251 int i; 252 253 if (intr < 0 || intr >= 16) 254 panic("invalid interrupt number"); 255 256 for (i = 0; i < MACE_NINTR; i++) 257 if (maceintrtab[i].func == NULL) { 258 maceintrtab[i].func = func; 259 maceintrtab[i].arg = arg; 260 maceintrtab[i].irq = (1 << intr); 261 maceintrtab[i].intrmask = level; 262 snprintf(maceintrtab[i].evname, 263 sizeof(maceintrtab[i].evname), 264 "intr %d lv 0x%x", intr, level); 265 evcnt_attach_dynamic(&maceintrtab[i].evcnt, 266 EVCNT_TYPE_INTR, NULL, 267 "mace", maceintrtab[i].evname); 268 break; 269 } 270 271 crime_intr_mask(intr); 272 aprint_debug("mace: established interrupt %d (level %x)\n", 273 intr, level); 274 return (void *)&maceintrtab[i]; 275 } 276 277 void 278 mace_intr_disestablish(void *cookie) 279 { 280 int intr = -1, level = 0, irq = 0, i; 281 282 for (i = 0; i < MACE_NINTR; i++) 283 if (&maceintrtab[i] == cookie) { 284 evcnt_detach(&maceintrtab[i].evcnt); 285 for (intr = 0; 286 maceintrtab[i].irq == (1 << intr); intr++); 287 level = maceintrtab[i].intrmask; 288 irq = maceintrtab[i].irq; 289 290 maceintrtab[i].irq = 0; 291 maceintrtab[i].intrmask = 0; 292 maceintrtab[i].func = NULL; 293 maceintrtab[i].arg = NULL; 294 memset(&maceintrtab[i].evcnt, 0, sizeof (struct evcnt)); 295 memset(&maceintrtab[i].evname, 0, 296 sizeof (maceintrtab[i].evname)); 297 break; 298 } 299 if (intr == -1) 300 panic("mace: lost maceintrtab"); 301 302 /* do not do an unmask when irq is shared. */ 303 for (i = 0; i < MACE_NINTR; i++) 304 if (maceintrtab[i].func != NULL && maceintrtab[i].irq == irq) 305 break; 306 if (i == MACE_NINTR) 307 crime_intr_unmask(intr); 308 aprint_debug("mace: disestablished interrupt %d (level %x)\n", 309 intr, level); 310 } 311 312 void 313 mace_intr(int irqs) 314 { 315 uint64_t isa_irq; 316 int i; 317 318 /* irq 4 is the ISA cascade interrupt. Must handle with care. */ 319 if (irqs & (1 << 4)) { 320 isa_irq = mips3_ld(MIPS_PHYS_TO_KSEG1(MACE_BASE 321 + MACE_ISA_INT_STATUS)); 322 for (i = 0; i < MACE_NINTR; i++) { 323 if ((maceintrtab[i].irq == (1 << 4)) && 324 (isa_irq & maceintrtab[i].intrmask)) { 325 (maceintrtab[i].func)(maceintrtab[i].arg); 326 maceintrtab[i].evcnt.ev_count++; 327 } 328 } 329 irqs &= ~(1 << 4); 330 } 331 332 for (i = 0; i < MACE_NINTR; i++) 333 if ((irqs & maceintrtab[i].irq)) { 334 (maceintrtab[i].func)(maceintrtab[i].arg); 335 maceintrtab[i].evcnt.ev_count++; 336 } 337 } 338 339 #if defined(BLINK) 340 static void 341 mace_blink(void *self) 342 { 343 struct mace_softc *sc = device_private(self); 344 register int s; 345 int value; 346 347 s = splhigh(); 348 value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 349 value ^= MACE_ISA_LED_GREEN; 350 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); 351 splx(s); 352 /* 353 * Blink rate is: 354 * full cycle every second if completely idle (loadav = 0) 355 * full cycle every 2 seconds if loadav = 1 356 * full cycle every 3 seconds if loadav = 2 357 * etc. 358 */ 359 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 360 callout_reset(&mace_blink_ch, s, mace_blink, sc); 361 362 } 363 #endif 364 365 #define CHIP mace_isa 366 #define CHIP_MEM /* defined */ 367 #define CHIP_ALIGN_STRIDE 8 368 #define CHIP_ACCESS_SIZE 8 369 #define CHIP_W1_BUS_START(v) 0x00000000UL 370 #define CHIP_W1_BUS_END(v) 0xffffffffUL 371 #define CHIP_W1_SYS_START(v) 0x00000000UL 372 #define CHIP_W1_SYS_END(v) 0xffffffffUL 373 374 #include <mips/mips/bus_space_alignstride_chipdep.c> 375
Indexes created Sat Sep 20 22:09:52 GMT 2025