1 /* $NetBSD: jzmmc.c,v 1.1 2026/07/26 20:15:17 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2017, 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Ingenic JZ4780 MMC/SD controller (MSC) driver. 31 * 32 * The driver has a few peculiarities related to CI20: 33 * - only MSC1 is supported 34 * - the pins must be muxed here 35 * - card detect is a plain GPIO on PF20 36 * - card power is a fixed always-on 3.3V rail 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: jzmmc.c,v 1.1 2026/07/26 20:15:17 rkujawa Exp $"); 41 42 #include "opt_ingenic.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/kernel.h> 48 #include <sys/proc.h> 49 #include <sys/bus.h> 50 #include <sys/mutex.h> 51 #include <sys/condvar.h> 52 53 #include <dev/sdmmc/sdmmcvar.h> 54 #include <dev/sdmmc/sdmmcchip.h> 55 #include <dev/sdmmc/sdmmcreg.h> 56 57 #include <mips/ingenic/ingenic_var.h> 58 #include <mips/ingenic/ingenic_regs.h> 59 60 /* 61 * SDMA descriptor 62 */ 63 #define JZMMC_NDESC SDMMC_MAXNSEGS 64 #define JZMMC_DESC_WORDS 4 65 #define JZMMC_DESC_SIZE (JZMMC_DESC_WORDS * 4) 66 #define JZMMC_DESC_NDA 0 67 #define JZMMC_DESC_DA 1 68 #define JZMMC_DESC_LEN 2 69 #define JZMMC_DESC_CMD 3 70 71 #ifdef JZMMC_DEBUG 72 #define DPRINTF printf 73 #else 74 #define DPRINTF while (0) printf 75 #endif 76 77 /* 78 * The CGU MSC1CDR divider runs off the MPLL, which u-boot programs to 79 * 1200MHz on the CI20 80 */ 81 #define JZMMC_MPLL_KHZ 1200000 /* should be configurable */ 82 #define JZMMC_CDR_DIV 11 83 #define JZMMC_DEVCLK_KHZ (JZMMC_MPLL_KHZ / ((JZMMC_CDR_DIV + 1) * 2)) 84 85 /* SD slot pins: PE20-23 = D0-D3, PE28 = CLK, PE29 = CMD, all function 1 */ 86 static const int jzmmc_sdslot_pins[] = { 20, 21, 22, 23, 28, 29 }; 87 #define JZMMC_GPIO_E 4 88 #define JZMMC_GPIO_F 5 89 #define JZMMC_CD_PIN 20 /* PF20, active low */ 90 91 struct jzmmc_softc { 92 device_t sc_dev; 93 bus_space_tag_t sc_bst; 94 bus_space_handle_t sc_bsh; 95 device_t sc_sdmmc; 96 void *sc_ih; 97 kmutex_t sc_intr_lock; 98 kcondvar_t sc_intr_cv; 99 bus_dma_tag_t sc_dmat; 100 bus_dmamap_t sc_desc_map; 101 bus_dma_segment_t sc_desc_seg; 102 uint32_t *sc_desc; /* uncached descriptor ring */ 103 uint32_t sc_widthbits; /* cached CMDAT bus width */ 104 u_int sc_dma_fails; /* silent errors */ 105 bool sc_inited; /* init sent */ 106 bool sc_use_intr; /* handler established */ 107 bool sc_use_dma; /* descriptor ring ready */ 108 }; 109 110 #define MR4(sc, r) bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (r)) 111 #define MW4(sc, r, v) bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (r), (v)) 112 #define MR2(sc, r) bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (r)) 113 #define MW2(sc, r, v) bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (r), (v)) 114 #define MW1(sc, r, v) bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (r), (v)) 115 116 #define JZMMC_FIFO_BURST 16 117 118 #define JZMMC_REG_SIZE 0x100 /* registers end at RTCNT, 0x5c */ 119 120 static int jzmmc_match(device_t, cfdata_t, void *); 121 static void jzmmc_attach(device_t, device_t, void *); 122 123 static int jzmmc_host_reset(sdmmc_chipset_handle_t); 124 static uint32_t jzmmc_host_ocr(sdmmc_chipset_handle_t); 125 static int jzmmc_host_maxblklen(sdmmc_chipset_handle_t); 126 static int jzmmc_card_detect(sdmmc_chipset_handle_t); 127 static int jzmmc_write_protect(sdmmc_chipset_handle_t); 128 static int jzmmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 129 static int jzmmc_bus_clock(sdmmc_chipset_handle_t, int); 130 static int jzmmc_bus_width(sdmmc_chipset_handle_t, int); 131 static int jzmmc_bus_rod(sdmmc_chipset_handle_t, int); 132 static void jzmmc_exec_command(sdmmc_chipset_handle_t, 133 struct sdmmc_command *); 134 static void jzmmc_card_enable_intr(sdmmc_chipset_handle_t, int); 135 static void jzmmc_card_intr_ack(sdmmc_chipset_handle_t); 136 137 static struct sdmmc_chip_functions jzmmc_chip_functions = { 138 .host_reset = jzmmc_host_reset, 139 .host_ocr = jzmmc_host_ocr, 140 .host_maxblklen = jzmmc_host_maxblklen, 141 .card_detect = jzmmc_card_detect, 142 .write_protect = jzmmc_write_protect, 143 .bus_power = jzmmc_bus_power, 144 .bus_clock = jzmmc_bus_clock, 145 .bus_width = jzmmc_bus_width, 146 .bus_rod = jzmmc_bus_rod, 147 .exec_command = jzmmc_exec_command, 148 .card_enable_intr = jzmmc_card_enable_intr, 149 .card_intr_ack = jzmmc_card_intr_ack, 150 }; 151 152 CFATTACH_DECL_NEW(jzmmc, sizeof(struct jzmmc_softc), 153 jzmmc_match, jzmmc_attach, NULL, NULL); 154 155 /* 156 * Polled fallback, used before the interrupt handler is established. 157 */ 158 static int 159 jzmmc_wait_iflg_poll(struct jzmmc_softc *sc, uint32_t mask, int timo_ms) 160 { 161 int us = timo_ms * 1000; 162 int spin; 163 164 for (spin = 200; spin > 0 && us > 0; spin--) { 165 if (MR4(sc, JZ_MSC_IFLG) & mask) 166 return 0; 167 delay(5); 168 us -= 5; 169 } 170 while (us > 0) { 171 if (MR4(sc, JZ_MSC_IFLG) & mask) 172 return 0; 173 kpause("jzmmcw", false, mstohz(10) ? mstohz(10) : 1, NULL); 174 us -= 10000; 175 } 176 return ETIMEDOUT; 177 } 178 179 /* 180 * Interrupt-driven wait 181 */ 182 static int 183 jzmmc_wait_iflg(struct jzmmc_softc *sc, uint32_t mask, int timo_ms) 184 { 185 int error, timo; 186 187 if (!sc->sc_use_intr || cold) { 188 error = jzmmc_wait_iflg_poll(sc, mask, timo_ms); 189 goto out; 190 } 191 192 mutex_enter(&sc->sc_intr_lock); 193 MW4(sc, JZ_MSC_IMASK, MR4(sc, JZ_MSC_IMASK) & ~mask); 194 timo = mstohz(timo_ms) ? mstohz(timo_ms) : 1; 195 while ((MR4(sc, JZ_MSC_IFLG) & mask) == 0) { 196 error = cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_lock, timo); 197 if (error != 0) 198 break; 199 } 200 MW4(sc, JZ_MSC_IMASK, MR4(sc, JZ_MSC_IMASK) | mask); 201 error = (MR4(sc, JZ_MSC_IFLG) & mask) ? 0 : ETIMEDOUT; 202 mutex_exit(&sc->sc_intr_lock); 203 out: 204 if (error != 0) { 205 DPRINTF("%s: timeout waiting for iflg %08x " 206 "(iflg %08x stat %08x)\n", 207 device_xname(sc->sc_dev), mask, MR4(sc, JZ_MSC_IFLG), 208 MR4(sc, JZ_MSC_STAT)); 209 } 210 return error; 211 } 212 213 static int 214 jzmmc_intr(void *arg) 215 { 216 struct jzmmc_softc *sc = arg; 217 uint32_t pend, imask; 218 219 mutex_enter(&sc->sc_intr_lock); 220 imask = MR4(sc, JZ_MSC_IMASK); 221 pend = MR4(sc, JZ_MSC_IFLG) & ~imask; 222 if (pend == 0) { 223 mutex_exit(&sc->sc_intr_lock); 224 return 0; 225 } 226 MW4(sc, JZ_MSC_IMASK, imask | pend); 227 cv_broadcast(&sc->sc_intr_cv); 228 mutex_exit(&sc->sc_intr_lock); 229 return 1; 230 } 231 232 static int 233 jzmmc_controller_reset(struct jzmmc_softc *sc) 234 { 235 int timo; 236 237 MW2(sc, JZ_MSC_CTRL, JZ_RESET); 238 delay(20); 239 for (timo = 1000; timo > 0; timo--) { 240 if ((MR4(sc, JZ_MSC_STAT) & JZ_IS_RESETTING) == 0) 241 break; 242 delay(10); 243 } 244 if (timo == 0) 245 return ETIMEDOUT; 246 247 /* mask all interrupts (we poll), ack any stale flags */ 248 MW4(sc, JZ_MSC_IMASK, 0xffffffff); 249 MW4(sc, JZ_MSC_IFLG, 0xffffffff); 250 /* generous hardware timeouts, in MSC_CLK cycles */ 251 MW2(sc, JZ_MSC_RESTO, 0xffff); 252 MW4(sc, JZ_MSC_RDTO, 0xffffffff); 253 /* keep the internal DMA engine off the FIFO between transfers */ 254 MW4(sc, JZ_MSC_DMAC, 0); 255 return 0; 256 } 257 258 /* 259 * Allocate the SDMA descriptor ring 260 */ 261 static int 262 jzmmc_dma_init(struct jzmmc_softc *sc) 263 { 264 int error, rseg; 265 void *kva; 266 267 error = bus_dmamem_alloc(sc->sc_dmat, JZMMC_NDESC * JZMMC_DESC_SIZE, 268 JZMMC_DESC_SIZE, 0, &sc->sc_desc_seg, 1, &rseg, BUS_DMA_WAITOK); 269 if (error != 0) 270 return error; 271 error = bus_dmamem_map(sc->sc_dmat, &sc->sc_desc_seg, rseg, 272 JZMMC_NDESC * JZMMC_DESC_SIZE, &kva, 273 BUS_DMA_WAITOK | BUS_DMA_COHERENT); 274 if (error != 0) 275 goto free; 276 error = bus_dmamap_create(sc->sc_dmat, JZMMC_NDESC * JZMMC_DESC_SIZE, 277 1, JZMMC_NDESC * JZMMC_DESC_SIZE, 0, BUS_DMA_WAITOK, 278 &sc->sc_desc_map); 279 if (error != 0) 280 goto unmap; 281 error = bus_dmamap_load(sc->sc_dmat, sc->sc_desc_map, kva, 282 JZMMC_NDESC * JZMMC_DESC_SIZE, NULL, BUS_DMA_WAITOK); 283 if (error != 0) 284 goto destroy; 285 sc->sc_desc = kva; 286 return 0; 287 288 destroy: 289 bus_dmamap_destroy(sc->sc_dmat, sc->sc_desc_map); 290 unmap: 291 bus_dmamem_unmap(sc->sc_dmat, kva, JZMMC_NDESC * JZMMC_DESC_SIZE); 292 free: 293 bus_dmamem_free(sc->sc_dmat, &sc->sc_desc_seg, rseg); 294 return error; 295 } 296 297 /* 298 * Build the descriptor chain for cmd's dmamap, one descriptor per 299 * segment, and hand it to the engine. 300 */ 301 static void 302 jzmmc_dma_prepare(struct jzmmc_softc *sc, struct sdmmc_command *cmd) 303 { 304 bus_dmamap_t map = cmd->c_dmamap; 305 const bus_addr_t ring = sc->sc_desc_map->dm_segs[0].ds_addr; 306 bus_size_t resid = cmd->c_datalen, len; 307 uint32_t *d; 308 int seg; 309 310 KASSERT(map->dm_nsegs > 0 && map->dm_nsegs <= JZMMC_NDESC); 311 KASSERT(map->dm_mapsize >= cmd->c_datalen); 312 for (seg = 0; resid > 0; seg++) { 313 KASSERT(seg < map->dm_nsegs); 314 KASSERT(((map->dm_segs[seg].ds_addr | 315 map->dm_segs[seg].ds_len) & 0x3) == 0); 316 len = MIN(map->dm_segs[seg].ds_len, resid); 317 resid -= len; 318 d = &sc->sc_desc[seg * JZMMC_DESC_WORDS]; 319 d[JZMMC_DESC_NDA] = resid == 0 ? 0 : 320 ring + (seg + 1) * JZMMC_DESC_SIZE; 321 d[JZMMC_DESC_DA] = map->dm_segs[seg].ds_addr; 322 d[JZMMC_DESC_LEN] = len; 323 d[JZMMC_DESC_CMD] = resid == 0 ? 324 (JZ_DMA_ENDI | JZ_DMA_LINK) : 0; 325 } 326 wbflush(); 327 MW4(sc, JZ_MSC_DMANDA, ring); 328 } 329 330 static int 331 jzmmc_match(device_t parent, cfdata_t match, void *aux) 332 { 333 struct apbus_attach_args *aa = aux; 334 335 if (strcmp(aa->aa_name, "jzmmc") != 0) 336 return 0; 337 if (aa->aa_addr != JZ_MSC1_BASE) 338 return 0; 339 return 1; 340 } 341 342 static void 343 jzmmc_attach(device_t parent, device_t self, void *aux) 344 { 345 struct jzmmc_softc *sc = device_private(self); 346 struct apbus_attach_args *aa = aux; 347 struct sdmmcbus_attach_args saa; 348 int error; 349 size_t i; 350 351 sc->sc_dev = self; 352 sc->sc_bst = aa->aa_bst; 353 sc->sc_dmat = aa->aa_dmat; 354 sc->sc_widthbits = JZ_BUS_1BIT; 355 sc->sc_inited = false; 356 357 aprint_naive("\n"); 358 aprint_normal(": SD/MMC controller\n"); 359 360 error = bus_space_map(aa->aa_bst, aa->aa_addr, JZMMC_REG_SIZE, 0, &sc->sc_bsh); 361 if (error != 0) { 362 aprint_error_dev(self, "can't map registers: %d\n", error); 363 return; 364 } 365 366 /* mux the SD-slot pins to MSC1 (port E function 1), CD as input */ 367 for (i = 0; i < __arraycount(jzmmc_sdslot_pins); i++) 368 gpio_as_dev1(JZMMC_GPIO_E, jzmmc_sdslot_pins[i]); 369 gpio_as_input(JZMMC_GPIO_F, JZMMC_CD_PIN); 370 371 /* device clock from the CGU: MPLL / ((div+1)*2) */ 372 error = ingenic_cdr_set(aa->aa_clockreg, 373 MSCCDR_MPLL | JZMMC_CDR_DIV); 374 if (error != 0) { 375 aprint_error_dev(self, "clock divider stuck busy\n"); 376 goto fail; 377 } 378 aprint_normal_dev(self, "device clock %d kHz (MPLL assumed %d kHz)\n", 379 JZMMC_DEVCLK_KHZ, JZMMC_MPLL_KHZ); 380 381 if (jzmmc_controller_reset(sc) != 0) { 382 aprint_error_dev(self, "controller stuck in reset, stat %08x\n", 383 MR4(sc, JZ_MSC_STAT)); 384 goto fail; 385 } 386 387 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_VM); 388 cv_init(&sc->sc_intr_cv, "jzmmcirq"); 389 390 /* 391 * All interrupts are masked (and stay masked outside of waits), 392 * so establishing the handler this early is safe. 393 */ 394 sc->sc_ih = evbmips_intr_establish(aa->aa_irq, jzmmc_intr, sc); 395 if (sc->sc_ih == NULL) 396 aprint_error_dev(self, "can't establish interrupt, polling\n"); 397 sc->sc_use_intr = sc->sc_ih != NULL; 398 399 error = jzmmc_dma_init(sc); 400 if (error != 0) 401 aprint_error_dev(self, 402 "can't set up DMA descriptors (%d), using PIO\n", error); 403 sc->sc_use_dma = error == 0; 404 405 aprint_normal_dev(self, "card %spresent\n", 406 jzmmc_card_detect(sc) ? "" : "not "); 407 408 memset(&saa, 0, sizeof(saa)); 409 saa.saa_busname = "sdmmc"; 410 saa.saa_sct = &jzmmc_chip_functions; 411 saa.saa_sch = sc; 412 saa.saa_dmat = aa->aa_dmat; 413 saa.saa_clkmin = JZMMC_DEVCLK_KHZ / 128; 414 /* 415 * 50MHz (CLKRT = 0) is only used for SD high-speed timing 416 */ 417 saa.saa_clkmax = JZMMC_DEVCLK_KHZ; 418 saa.saa_caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_POLL_CARD_DET | 419 SMC_CAPS_SD_HIGHSPEED | SMC_CAPS_AUTO_STOP; 420 if (sc->sc_use_dma) { 421 saa.saa_caps |= SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA; 422 /* the framework bounces buffers this can't express */ 423 saa.saa_dma_align_mask = 0x3; 424 } 425 426 sc->sc_sdmmc = config_found(self, &saa, NULL, CFARGS_NONE); 427 return; 428 429 fail: 430 bus_space_unmap(aa->aa_bst, sc->sc_bsh, JZMMC_REG_SIZE); 431 } 432 433 static int 434 jzmmc_host_reset(sdmmc_chipset_handle_t sch) 435 { 436 struct jzmmc_softc *sc = sch; 437 438 sc->sc_inited = false; 439 return jzmmc_controller_reset(sc); 440 } 441 442 static uint32_t 443 jzmmc_host_ocr(sdmmc_chipset_handle_t sch) 444 { 445 446 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V; 447 } 448 449 static int 450 jzmmc_host_maxblklen(sdmmc_chipset_handle_t sch) 451 { 452 453 return 512; 454 } 455 456 static int 457 jzmmc_card_detect(sdmmc_chipset_handle_t sch) 458 { 459 460 /* PF20, active low */ 461 return !gpio_get(JZMMC_GPIO_F, JZMMC_CD_PIN); 462 } 463 464 static int 465 jzmmc_write_protect(sdmmc_chipset_handle_t sch) 466 { 467 468 return 0; /* no write-protect switch wired up */ 469 } 470 471 static int 472 jzmmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 473 { 474 475 return 0; /* fixed always-on 3.3V */ 476 } 477 478 static int 479 jzmmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 480 { 481 struct jzmmc_softc *sc = sch; 482 int n; 483 484 if (freq == 0) { 485 MW2(sc, JZ_MSC_CTRL, JZ_CLOCK_STOP); 486 return 0; 487 } 488 /* smallest 2^n divider with devclk/2^n <= freq (in kHz) */ 489 for (n = 0; n < 7; n++) { 490 if ((JZMMC_DEVCLK_KHZ >> n) <= freq) 491 break; 492 } 493 MW2(sc, JZ_MSC_CLKRT, n); 494 /* 495 * Above 25MHz the controller MUST drive CMD/DAT a quarter clock 496 * early and sample on the rising edge... without this every 497 * transfer fails with CRC errors. 498 */ 499 if ((JZMMC_DEVCLK_KHZ >> n) > 25000) 500 MW4(sc, JZ_MSC_LPM, JZ_RISING_4 | JZ_SMP_SEL | JZ_LPM); 501 else 502 MW4(sc, JZ_MSC_LPM, 0); 503 DPRINTF("%s: clock req %d kHz -> CLKRT %d (%d kHz)\n", 504 device_xname(sc->sc_dev), freq, n, JZMMC_DEVCLK_KHZ >> n); 505 return 0; 506 } 507 508 static int 509 jzmmc_bus_width(sdmmc_chipset_handle_t sch, int width) 510 { 511 struct jzmmc_softc *sc = sch; 512 513 switch (width) { 514 case 1: 515 sc->sc_widthbits = JZ_BUS_1BIT; 516 break; 517 case 4: 518 sc->sc_widthbits = JZ_BUS_4BIT; 519 break; 520 default: 521 return EINVAL; 522 } 523 return 0; 524 } 525 526 static int 527 jzmmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 528 { 529 530 return ENOTSUP; 531 } 532 533 static void 534 jzmmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 535 { 536 /* no SDIO support */ 537 } 538 539 static void 540 jzmmc_card_intr_ack(sdmmc_chipset_handle_t sch) 541 { 542 /* no SDIO support */ 543 } 544 545 static void 546 jzmmc_read_response(struct jzmmc_softc *sc, struct sdmmc_command *cmd) 547 { 548 uint32_t b[4]; 549 uint16_t r[9]; 550 int i; 551 552 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 553 return; 554 555 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 556 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, JZ_MSC_RES, 557 r, 9); 558 /* byte-carried halfwords: b[i] spans r[2i]..r[2i+2] */ 559 for (i = 0; i < 4; i++) { 560 b[i] = ((uint32_t)r[2 * i] << 24) | 561 ((uint32_t)r[2 * i + 1] << 8) | 562 ((uint32_t)r[2 * i + 2] >> 8); 563 } 564 /* b[0] = bits 127:96 of the payload ... b[3] = bits 31:0 */ 565 cmd->c_resp[0] = (b[2] << 24) | (b[3] >> 8); 566 cmd->c_resp[1] = (b[1] << 24) | (b[2] >> 8); 567 cmd->c_resp[2] = (b[0] << 24) | (b[1] >> 8); 568 cmd->c_resp[3] = b[0] >> 8; 569 DPRINTF("%s: R2 raw %08x %08x %08x %08x -> resp %08x %08x %08x %08x\n", 570 device_xname(sc->sc_dev), b[0], b[1], b[2], b[3], 571 cmd->c_resp[0], cmd->c_resp[1], cmd->c_resp[2], 572 cmd->c_resp[3]); 573 } else { 574 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, JZ_MSC_RES, 575 r, 3); 576 cmd->c_resp[0] = ((uint32_t)r[0] << 24) | 577 ((uint32_t)r[1] << 8) | (r[2] & 0xff); 578 } 579 } 580 581 static int 582 jzmmc_pio_read(struct jzmmc_softc *sc, struct sdmmc_command *cmd) 583 { 584 uint32_t *p = cmd->c_data; 585 size_t nwords = cmd->c_datalen / 4; 586 uint32_t stat; 587 int guard, spin; 588 589 DPRINTF("%s: pio_read %zu words, rtcnt %u iflg %08x stat %08x\n", 590 device_xname(sc->sc_dev), nwords, MR4(sc, JZ_MSC_RTCNT), 591 MR4(sc, JZ_MSC_IFLG), MR4(sc, JZ_MSC_STAT)); 592 guard = 100; /* ~1s: 100 x 10ms kpause */ 593 spin = 2000; 594 while (nwords > 0) { 595 stat = MR4(sc, JZ_MSC_STAT); 596 if (stat & JZ_TIME_OUT_READ) 597 return ETIMEDOUT; 598 if (stat & JZ_CRC_READ_ERR) 599 return EIO; 600 /* 601 * the FIFO carries a byte stream, which a byte-swapping 602 * bus_space must not reorder. Burst when the trigger 603 * level guarantees a full JZMMC_FIFO_BURST, drain 604 * word-wise below it. 605 */ 606 if (nwords >= JZMMC_FIFO_BURST && 607 (MR4(sc, JZ_MSC_IFLG) & JZ_INT_RXFIFO_RD_REQ)) { 608 bus_space_read_multi_stream_4(sc->sc_bst, sc->sc_bsh, 609 JZ_MSC_RXFIFO, p, JZMMC_FIFO_BURST); 610 p += JZMMC_FIFO_BURST; 611 nwords -= JZMMC_FIFO_BURST; 612 spin = 2000; 613 continue; 614 } 615 if ((stat & JZ_DATA_FIFO_EMPTY) == 0) { 616 bus_space_read_multi_stream_4(sc->sc_bst, sc->sc_bsh, 617 JZ_MSC_RXFIFO, p, 1); 618 p++; 619 nwords--; 620 spin = 2000; 621 continue; 622 } 623 if (spin > 0) { 624 spin--; 625 delay(1); 626 } else { 627 if (--guard == 0) 628 return ETIMEDOUT; 629 kpause("jzmmcr", false, 630 mstohz(10) ? mstohz(10) : 1, NULL); 631 } 632 } 633 return 0; 634 } 635 636 static int 637 jzmmc_pio_write(struct jzmmc_softc *sc, struct sdmmc_command *cmd) 638 { 639 const uint32_t *p = cmd->c_data; 640 size_t nwords = cmd->c_datalen / 4; 641 uint32_t stat; 642 int guard, spin; 643 644 guard = 100; 645 spin = 2000; 646 while (nwords > 0) { 647 stat = MR4(sc, JZ_MSC_STAT); 648 if ((stat & JZ_CRC_WRITE_ERR_M) != JZ_CRC_WRITE_OK) 649 return EIO; 650 if (nwords >= JZMMC_FIFO_BURST && 651 (MR4(sc, JZ_MSC_IFLG) & JZ_INT_TXFIFO_WR_REQ)) { 652 bus_space_write_multi_stream_4(sc->sc_bst, sc->sc_bsh, 653 JZ_MSC_TXFIFO, p, JZMMC_FIFO_BURST); 654 p += JZMMC_FIFO_BURST; 655 nwords -= JZMMC_FIFO_BURST; 656 spin = 2000; 657 continue; 658 } 659 if ((stat & JZ_DATA_FIFO_FULL) == 0) { 660 bus_space_write_multi_stream_4(sc->sc_bst, sc->sc_bsh, 661 JZ_MSC_TXFIFO, p, 1); 662 p++; 663 nwords--; 664 spin = 2000; 665 continue; 666 } 667 if (spin > 0) { 668 spin--; 669 delay(1); 670 } else { 671 if (--guard == 0) 672 return ETIMEDOUT; 673 kpause("jzmmcw", false, 674 mstohz(10) ? mstohz(10) : 1, NULL); 675 } 676 } 677 return 0; 678 } 679 680 static int 681 jzmmc_dma_wait_read(struct jzmmc_softc *sc, struct sdmmc_command *cmd) 682 { 683 const uint32_t errbits = JZ_INT_TIMEOUT_READ | JZ_INT_CRC_READ_ERR; 684 uint32_t stat; 685 int error; 686 687 error = jzmmc_wait_iflg(sc, JZ_INT_DMAEND | errbits, 5000); 688 stat = MR4(sc, JZ_MSC_STAT); 689 if (error != 0) { 690 if ((stat & (JZ_TIME_OUT_READ | JZ_CRC_READ_ERR)) == 0) { 691 if (sc->sc_dma_fails++ < 5) 692 device_printf(sc->sc_dev, 693 "silent DMA fail: dmanda %08x " 694 "dmada %08x dmalen %08x dmacmd %08x " 695 "snob %d\n", 696 MR4(sc, JZ_MSC_DMANDA), 697 MR4(sc, JZ_MSC_DMADA), 698 MR4(sc, JZ_MSC_DMALEN), 699 MR4(sc, JZ_MSC_DMACMD), 700 MR2(sc, JZ_MSC_SNOB)); 701 } 702 return error; 703 } 704 MW4(sc, JZ_MSC_IFLG, 705 MR4(sc, JZ_MSC_IFLG) & (JZ_INT_DMAEND | errbits)); 706 if (stat & JZ_TIME_OUT_READ) 707 return ETIMEDOUT; 708 if (stat & JZ_CRC_READ_ERR) 709 return EIO; 710 return 0; 711 } 712 713 static void 714 jzmmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 715 { 716 struct jzmmc_softc *sc = sch; 717 uint32_t cmdat, stat, iflg; 718 bool dma = false, autostop = false; 719 int error = 0; 720 721 #ifdef JZMMC_DEBUG_VERBOSE 722 printf("%s: CMD%d arg %08x flags %#x datalen %d\n", 723 device_xname(sc->sc_dev), cmd->c_opcode, cmd->c_arg, 724 cmd->c_flags, cmd->c_datalen); 725 #endif 726 727 cmdat = sc->sc_widthbits; 728 729 /* response format */ 730 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)) 731 cmdat |= JZ_RES_NONE; 732 else if (ISSET(cmd->c_flags, SCF_RSP_136)) 733 cmdat |= JZ_RES_R2; 734 else if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) 735 cmdat |= JZ_RES_R3; 736 else { 737 cmdat |= JZ_RES_R1; 738 if (ISSET(cmd->c_flags, SCF_RSP_BSY)) 739 cmdat |= JZ_BUSY; 740 } 741 742 if (!sc->sc_inited) { 743 cmdat |= JZ_INIT; 744 sc->sc_inited = true; 745 } 746 747 if (cmd->c_datalen > 0) { 748 if (cmd->c_blklen == 0 || (cmd->c_datalen % 4) != 0) { 749 error = EINVAL; 750 goto done; 751 } 752 cmdat |= JZ_DATA_EN; 753 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) 754 cmdat |= JZ_WRITE; 755 dma = sc->sc_use_dma && cmd->c_dmamap != NULL; 756 if (dma) { 757 jzmmc_dma_prepare(sc, cmd); 758 } else { 759 /* 760 * PIO: the internal descriptor DMA must be explicitly 761 * disabled or it owns the data FIFO's read port 762 */ 763 MW4(sc, JZ_MSC_DMAC, 0); 764 } 765 MW2(sc, JZ_MSC_BLKLEN, cmd->c_blklen); 766 MW2(sc, JZ_MSC_NOB, cmd->c_datalen / cmd->c_blklen); 767 /* 768 * Multi-block transfers need STOP_TRANSMISSION 769 */ 770 if (cmd->c_datalen > cmd->c_blklen) { 771 cmdat |= JZ_AUTO_CMD12; 772 autostop = true; 773 } 774 } 775 776 MW4(sc, JZ_MSC_IFLG, 0xffffffff); /* ack stale flags */ 777 MW1(sc, JZ_MSC_CMD, cmd->c_opcode); 778 MW4(sc, JZ_MSC_ARG, cmd->c_arg); 779 MW4(sc, JZ_MSC_CMDAT, cmdat); 780 MW2(sc, JZ_MSC_CTRL, JZ_CLOCK_START | JZ_START_OP); 781 /* 782 * The engine may be enabled only once the operation has started 783 */ 784 if (dma) 785 MW4(sc, JZ_MSC_DMAC, JZ_INCR_16 | JZ_DMAEN); 786 787 788 error = jzmmc_wait_iflg(sc, JZ_INT_EMD_CMD_RES, 200); 789 if (error != 0) 790 goto done; 791 /* 792 * Snapshot both status views BEFORE acknowledging anything 793 */ 794 iflg = MR4(sc, JZ_MSC_IFLG); 795 stat = MR4(sc, JZ_MSC_STAT); 796 if ((stat & JZ_TIME_OUT_RES) || (iflg & JZ_INT_TIMEOUT_RES)) { 797 MW4(sc, JZ_MSC_IFLG, 798 JZ_INT_EMD_CMD_RES | JZ_INT_TIMEOUT_RES); 799 /* 800 * ensure that we don't get phantom cards 801 */ 802 error = ETIMEDOUT; 803 goto done; 804 } 805 MW4(sc, JZ_MSC_IFLG, JZ_INT_EMD_CMD_RES); 806 if ((stat & JZ_CRC_RES_ERR) && ISSET(cmd->c_flags, SCF_RSP_CRC)) { 807 error = EIO; 808 goto done; 809 } 810 811 jzmmc_read_response(sc, cmd); 812 813 if (cmd->c_datalen > 0) { 814 if (dma) { 815 /* DMA writes complete via the common tail below */ 816 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 817 error = jzmmc_dma_wait_read(sc, cmd); 818 } else if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 819 error = jzmmc_pio_read(sc, cmd); 820 } else { 821 error = jzmmc_pio_write(sc, cmd); 822 } 823 #ifdef JZMMC_DEBUG 824 if (error == 0 && cmd->c_datalen <= 8 && !dma && 825 ISSET(cmd->c_flags, SCF_CMD_READ)) { 826 const uint8_t *db = cmd->c_data; 827 printf("%s: CMD%d data:", device_xname(sc->sc_dev), 828 cmd->c_opcode); 829 for (size_t j = 0; j < cmd->c_datalen; j++) 830 printf(" %02x", db[j]); 831 printf("\n"); 832 } 833 #endif 834 if (error != 0) 835 goto done; 836 837 error = jzmmc_wait_iflg(sc, JZ_INT_DATA_TRAN_DONE, 5000); 838 if (error != 0) 839 goto done; 840 MW4(sc, JZ_MSC_IFLG, JZ_INT_DATA_TRAN_DONE); 841 842 if (autostop) { 843 /* controller-generated CMD12 (and its response) */ 844 error = jzmmc_wait_iflg(sc, 845 JZ_INT_AUTO_CMD12_DONE, 5000); 846 if (error != 0) 847 goto done; 848 MW4(sc, JZ_MSC_IFLG, JZ_INT_AUTO_CMD12_DONE); 849 } 850 851 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 852 /* wait for the card to finish programming */ 853 error = jzmmc_wait_iflg(sc, JZ_INT_PRG_DONE, 5000); 854 if (error != 0) 855 goto done; 856 MW4(sc, JZ_MSC_IFLG, JZ_INT_PRG_DONE); 857 stat = MR4(sc, JZ_MSC_STAT); 858 if ((stat & JZ_CRC_WRITE_ERR_M) != JZ_CRC_WRITE_OK) 859 error = EIO; 860 } 861 /* 862 * with the transfer fully over, take the engine off the FIFO 863 */ 864 if (dma) 865 MW4(sc, JZ_MSC_DMAC, 0); 866 } 867 868 done: 869 if (error != 0) { 870 DPRINTF("%s: CMD%d error %d (stat %08x iflg %08x snob %d)\n", 871 device_xname(sc->sc_dev), cmd->c_opcode, error, 872 MR4(sc, JZ_MSC_STAT), MR4(sc, JZ_MSC_IFLG), 873 MR2(sc, JZ_MSC_SNOB)); 874 if (dma) 875 MW4(sc, JZ_MSC_DMAC, 0); 876 /* 877 * Reset the controller so a failed command doesn't 878 * break the following ones. 879 */ 880 jzmmc_controller_reset(sc); 881 } 882 cmd->c_error = error; 883 SET(cmd->c_flags, SCF_ITSDONE); 884 } 885 886
Indexes created Sun Aug 09 00:24:28 UTC 2026