| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_combo_phy.h | 20 int lane_count, bool lane_reversal);
|
| intel_dp_link_training.c | 52 for (lane = 0; lane < intel_dp->lane_count; lane++) {
90 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
91 len = intel_dp->lane_count + 1;
117 intel_dp->train_set, intel_dp->lane_count);
119 return ret == intel_dp->lane_count;
126 for (lane = 0; lane < intel_dp->lane_count; lane++)
157 link_config[1] = intel_dp->lane_count;
205 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
317 intel_dp->lane_count)) {
325 intel_dp->lane_count)) {
[all...] |
| intel_dp.h | 53 int link_rate, u8 lane_count,
56 int link_rate, u8 lane_count);
128 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
130 return ~((1 << lane_count) - 1) & 0xf;
|
| intel_dpio_phy.c | 579 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
581 switch (lane_count) {
589 MISSING_CASE(lane_count);
666 if (intel_crtc->config->lane_count > 2) {
679 if (intel_crtc->config->lane_count > 2) {
687 for (i = 0; i < intel_crtc->config->lane_count; i++) {
695 for (i = 0; i < intel_crtc->config->lane_count; i++) {
718 for (i = 0; i < intel_crtc->config->lane_count; i++) {
732 if (intel_crtc->config->lane_count > 2) {
758 if (crtc_state->lane_count > 2)
[all...] |
| intel_dpio_phy.h | 31 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
|
| intel_combo_phy.c | 221 int lane_count, bool lane_reversal)
229 switch (lane_count) {
240 MISSING_CASE(lane_count);
247 switch (lane_count) {
257 MISSING_CASE(lane_count);
|
| vlv_dsi.c | 48 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
52 8 * 100), lane_count);
56 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
59 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
1043 unsigned int lane_count = intel_dsi->lane_count; local in function:bxt_dsi_get_pipe_config
1092 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1094 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1096 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1146 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1238 unsigned int lane_count = intel_dsi->lane_count; local in function:set_dsi_timings
[all...] |
| vlv_dsi_pll.c | 49 int lane_count)
56 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
130 intel_dsi->lane_count);
318 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
339 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
468 intel_dsi->lane_count);
|
| intel_dsi.c | 21 return intel_dsi->pclk * bpp / intel_dsi->lane_count;
|
| intel_dsi.h | 72 unsigned int lane_count; member in struct:intel_dsi
|
| intel_dp.c | 427 u8 lane_count)
438 if (lane_count == 0 ||
439 lane_count > intel_dp_max_lane_count(intel_dp))
447 u8 lane_count)
454 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
462 int link_rate, u8 lane_count)
473 lane_count)) {
478 intel_dp->max_link_lane_count = lane_count;
479 } else if (lane_count > 1) {
483 lane_count >> 1))
2013 int bpp, clock, lane_count; local in function:intel_dp_compute_link_config_wide
[all...] |
| intel_ddi.c | 1252 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1906 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1917 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
2514 width = intel_dp->lane_count;
2640 width = intel_dp->lane_count;
3202 width = crtc_state->lane_count;
3402 crtc_state->lane_count, is_mst);
3486 crtc_state->lane_count,
3547 crtc_state->lane_count, is_mst);
3578 crtc_state->lane_count,
[all...] |
| intel_dp_mst.c | 62 crtc_state->lane_count = limits->max_lane_count;
86 crtc_state->lane_count,
205 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_dp.c | 145 lt_settings->link_settings.lane_count;
180 lt_settings->link_settings.lane_count,
190 lt_settings->link_settings.lane_count,
279 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
296 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
388 for (lane = 0; lane < src.link_settings.lane_count; lane++) {
450 for (lane = 1; lane < link_training_setting->link_settings.lane_count;
508 max_lt_setting->link_settings.lane_count =
509 link_training_setting->link_settings.lane_count;
514 link_training_setting->link_settings.lane_count;
744 enum dc_lane_count lane_count = local in function:perform_post_lt_adj_req_sequence
880 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local in function:perform_channel_equalization_sequence
962 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local in function:perform_clock_recovery_sequence
[all...] |
| amdgpu_dc_link.c | 551 link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
1569 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
3316 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3335 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3379 link_bw_kbps *= link_setting->lane_count;
3413 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/ |
| amdgpu_dm_debugfs.c | 42 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
66 * echo <lane_count> <link_rate> > link_settings
105 link->cur_link_settings.lane_count,
112 link->verified_link_cap.lane_count,
119 link->reported_link_cap.lane_count,
126 link->preferred_link_setting.lane_count,
161 /* 0: lane_count; 1: link_rate */
231 /* save user force lane_count, link_rate to preferred settings
235 prefer_link_settings.lane_count = param[0];
264 * from lane_count, link_rate to figure which DP-x is for display to be worke
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 160 cfg->link_settings.lane_count =
161 stream->link->cur_link_settings.lane_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_link_encoder.c | 219 if (!value && link_settings->lane_count > LANE_COUNT_TWO)
220 link_settings->lane_count = LANE_COUNT_TWO;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_link_encoder.c | 491 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
1012 cntl.lanes_number = link_settings->lane_count;
1051 cntl.lanes_number = link_settings->lane_count;
1130 cntl.lanes_number = link_settings->link_settings.lane_count;
1135 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
|
| dce_clk_mgr.c | 532 cfg->link_settings.lane_count =
533 stream->link->cur_link_settings.lane_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_link_encoder.c | 501 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
974 cntl.lanes_number = link_settings->lane_count;
1013 cntl.lanes_number = link_settings->lane_count;
1096 cntl.lanes_number = link_settings->link_settings.lane_count;
1101 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
|
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dp_helper.c | 71 int lane_count)
81 for (lane = 0; lane < lane_count; lane++) {
91 int lane_count)
96 for (lane = 0; lane < lane_count; lane++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_dp.c | 212 int lane_count,
219 for (lane = 0; lane < lane_count; lane++) {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_link_encoder.c | 220 for (i = 0; i < link_settings->lane_count; i++)
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc_dp_types.h | 103 enum dc_lane_count lane_count; member in struct:dc_link_settings
|
