| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/ |
| imx6q-display5-tianma-tm070-1280x768.dts | 47 lvds0: lvds-channel@0 {
|
| imx6dl-aristainetos2_7.dts | 81 lvds-channel@0 {
|
| imx6q-b450v3.dts | 71 lvds0: lvds-channel@0 {
|
| imx6q-b650v3.dts | 71 lvds0: lvds-channel@0 {
|
| imx53-tx53-x13x.dts | 53 model = "Ka-Ro electronics TX53 module (LVDS)";
186 lvds0: lvds-channel@0 {
228 lvds1: lvds-channel@1 {
|
| imx6qdl-tx6-lvds.dtsi | 117 lvds0: lvds-channel@0 {
210 lvds1: lvds-channel@1 {
|
| imx6q-b850v3.dts | 60 lvds0: lvds-channel@0 {
|
| imx6qdl-savageboard.dtsi | 128 lvds-channel@0 {
|
| imx6q-display5.dtsi | 90 reg_lvds: regulator-lvds {
388 lvds0: lvds-channel@0 {
|
| imx6q-pistachio.dts | 125 backlight_lvds: backlight-lvds {
558 lvds-channel@1 {
|
| imx6q-novena.dts | 151 reg_lvds_lcd: regulator-lvds-lcd {
153 regulator-name = "lcd-lvds-power";
451 lvds-channel@0 {
|
| imx6q-ba16.dtsi | 105 reg_lvds: regulator-lvds {
|
| imx6q-evi.dts | 189 lvds0: lvds-channel@0 {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| amdgpu_bios_parser.c | 1005 /* for SS_Info table only support DP and LVDS */
1217 ATOM_LVDS_INFO_V12 *lvds; local
1225 lvds =
1228 if (!lvds)
1231 if (1 != lvds->sHeader.ucTableFormatRevision
1232 || 2 > lvds->sHeader.ucTableContentRevision)
1239 le16_to_cpu(lvds->sLCDTiming.usPixClk) * 10;
1242 le16_to_cpu(lvds->sLCDTiming.usHActive);
1244 * borders duing this translation, but LVDS generally*/
1246 * now. May need to revisit if we ever have LVDS with borders*
1336 ATOM_LCD_INFO_V13 *lvds; local
[all...] |
| amdgpu_bios_parser2.c | 692 /* TODO LVDS not support anymore? */
778 /* TODO LVDS not support anymore? */
859 struct lcd_info_v2_1 *lvds; local
867 lvds = GET_IMAGE(struct lcd_info_v2_1, DATA_TABLES(lcd_info));
869 if (!lvds)
873 if (!((lvds->table_header.format_revision == 2)
874 && (lvds->table_header.content_revision >= 1)))
880 info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
882 info->lcd_timing.horizontal_addressable = le16_to_cpu(lvds->lcd_timing.h_active);
884 * subtractingborders duing this translation, but LVDS generall
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_legacy_encoders.c | 74 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; local
75 panel_pwr_delay = lvds->panel_pwr_delay;
76 if (lvds->bl_dev)
77 backlight_level = lvds->backlight_level;
79 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; local
80 panel_pwr_delay = lvds->panel_pwr_delay;
81 if (lvds->bl_dev)
82 backlight_level = lvds->backlight_level;
86 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
155 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv local
158 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; local
212 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; local
306 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; local
313 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; local
444 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; local
447 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; local
475 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; local
479 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; local
[all...] |
| radeon_combios.c | 1112 struct radeon_encoder_lvds *lvds = NULL; local
1117 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1119 if (!lvds)
1126 lvds->panel_pwr_delay = 200;
1127 lvds->panel_vcc_delay = 2000;
1129 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1130 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1131 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1134 lvds->native_mode.vdisplay =
1138 lvds->native_mode.vdisplay
1187 struct radeon_encoder_lvds *lvds = NULL; local
[all...] |
| radeon_atombios.c | 335 /* Falcon NW laptop lists vga ddc line for LVDS */
424 * side and leaves no crtcs for LVDS or VGA.
1042 /* make sure not to combine LVDS */
1635 struct radeon_encoder_atom_dig *lvds = NULL; local
1642 lvds =
1645 if (!lvds)
1648 lvds->native_mode.clock =
1650 lvds->native_mode.hdisplay =
1652 lvds->native_mode.vdisplay =
1654 lvds->native_mode.htotal = lvds->native_mode.hdisplay
[all...] |
| radeon_legacy_crtc.c | 815 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; local
816 if (lvds) {
817 if (lvds->use_bios_dividers) {
818 pll_ref_div = lvds->panel_ref_divider;
819 pll_fb_post_div = (lvds->panel_fb_divider |
820 (lvds->panel_post_divider << 16));
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| Makefile | 146 imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo
147 dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtb
161 imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo
163 dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb
202 imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo
203 imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_encoders.c | 258 DRM_INFO("amdgpu atom LVDS backlight unloaded\n");
565 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
2014 struct amdgpu_encoder_atom_dig *lvds = NULL; local
2021 lvds =
2024 if (!lvds)
2027 lvds->native_mode.clock =
2029 lvds->native_mode.hdisplay =
2031 lvds->native_mode.vdisplay =
2033 lvds->native_mode.htotal = lvds->native_mode.hdisplay
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| nouveau_dispnv50_disp.c | 1586 struct nv50_disp_sor_lvds_script_v0 lvds; member in struct:__anon5143
1587 } lvds = { local
1630 lvds.lvds.script |= 0x0100;
1632 lvds.lvds.script |= 0x0200;
1636 lvds.lvds.script |= 0x0100;
1639 lvds.lvds.script |= 0x0100
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_lvds.c | 55 /* Private structure for the integrated LVDS support */
200 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
287 * Set the dithering flag on LVDS as needed, note that there is no
288 * special lvds dither control bit on pch-split platforms, dithering is
293 * Bspec wording suggests that LVDS port dithering only exists
406 DRM_ERROR("Can't support LVDS on pipe A\n");
416 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
506 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
510 /* These systems claim to have LVDS, but really don't */
725 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident)
829 u32 lvds; local
[all...] |
| /src/sys/dev/pci/ |
| radeonfb.c | 1022 /* Initialise delayed lvds operations for backlight. */
2402 /* should probably leave those alone on non-LVDS */
4578 uint32_t lvds; local
4612 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL);
4613 lvds &= ~RADEON_LVDS_DISPLAY_DIS;
4614 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) {
4615 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON;
4616 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN;
4617 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
[all...] |
| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_drv.h | 141 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; member in struct:drm_i915_private
|
