HomeSort by: relevance | last modified time | path
    Searched refs:max_backends_per_se (Results 1 - 19 of 19) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ni.c 917 rdev->config.cayman.max_backends_per_se = 4;
955 rdev->config.cayman.max_backends_per_se = 2;
969 rdev->config.cayman.max_backends_per_se = 2;
983 rdev->config.cayman.max_backends_per_se = 1;
990 rdev->config.cayman.max_backends_per_se = 1;
1111 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1115 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1145 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1157 rdev->config.cayman.max_backends_per_se *
radeon_kms.c 349 *value = rdev->config.cik.max_backends_per_se *
352 *value = rdev->config.si.max_backends_per_se *
355 *value = rdev->config.cayman.max_backends_per_se *
radeon_si.c 3115 rdev->config.si.max_backends_per_se = 4;
3132 rdev->config.si.max_backends_per_se = 4;
3150 rdev->config.si.max_backends_per_se = 4;
3167 rdev->config.si.max_backends_per_se = 2;
3184 rdev->config.si.max_backends_per_se = 1;
3301 rdev->config.si.max_backends_per_se);
radeon.h 2141 unsigned max_backends_per_se; member in struct:cayman_asic
2180 unsigned max_backends_per_se; member in struct:si_asic
2211 unsigned max_backends_per_se; member in struct:cik_asic
radeon_cik.c 2356 u32 num_rbs = rdev->config.cik.max_backends_per_se *
3209 rdev->config.cik.max_backends_per_se = 2;
3226 rdev->config.cik.max_backends_per_se = 4;
3242 rdev->config.cik.max_backends_per_se = 2;
3262 rdev->config.cik.max_backends_per_se = 1;
3364 rdev->config.cik.max_backends_per_se);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_atomfirmware.c 450 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
amdgpu_gfx.h 138 unsigned max_backends_per_se; member in struct:amdgpu_gfx_config
amdgpu_discovery.c 396 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
amdgpu_gfx_v6_0.c 1340 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1474 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1493 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1595 adev->gfx.config.max_backends_per_se = 4;
1612 adev->gfx.config.max_backends_per_se = 4;
1629 adev->gfx.config.max_backends_per_se = 4;
1646 adev->gfx.config.max_backends_per_se = 2;
1663 adev->gfx.config.max_backends_per_se = 1;
amdgpu_gfx_v7_0.c 1639 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1801 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1819 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
4279 adev->gfx.config.max_backends_per_se = 2;
4296 adev->gfx.config.max_backends_per_se = 4;
4312 adev->gfx.config.max_backends_per_se = 2;
4332 adev->gfx.config.max_backends_per_se = 1;
amdgpu_gfx_v8_0.c 1699 adev->gfx.config.max_backends_per_se = 2;
1716 adev->gfx.config.max_backends_per_se = 4;
1763 adev->gfx.config.max_backends_per_se = 2;
1779 adev->gfx.config.max_backends_per_se = 2;
1796 adev->gfx.config.max_backends_per_se = 1;
1814 adev->gfx.config.max_backends_per_se = 2;
3460 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3622 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3640 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
amdgpu_debugfs.c 566 config[no_regs++] = adev->gfx.config.max_backends_per_se;
amdgpu_atombios.c 736 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
amdgpu_kms.c 717 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
amdgpu_gfx_v10_0.c 1532 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1543 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
amdgpu_gfx_v9_0.c 2369 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
2380 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
amdgpu_device.c 1684 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
atomfirmware.h 1230 uint8_t max_backends_per_se; member in struct:atom_gfx_info_v2_2
1250 uint8_t max_backends_per_se; member in struct:atom_gfx_info_v2_3
1275 uint8_t max_backends_per_se; member in struct:atom_gfx_info_v2_4
atombios.h 5656 UCHAR max_backends_per_se; member in struct:_ATOM_GFX_INFO_V2_1

Completed in 74 milliseconds