| /src/sys/arch/arm/at91/ |
| at91pmc.c | 55 uint64_t mclk, pllaclk, pllbclk, pclk, mstclk; local
64 mclk = ((reg & PMC_MCFR_MAINF) * SLOW_CLOCK) / 16U;
67 if (((mclk / 1000) % 1000) >= 990) {
68 mclk += 1000000U - (mclk % 1000000U);
69 } else if (((mclk / 1000) % 1000) <= 10) {
70 mclk -= (mclk % 1000000U);
77 pllaclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1);
83 pllbclk = mclk * (((reg & PMC_PLL_MUL) >> PMC_PLL_MUL_SHIFT) + 1)
[all...] |
| /src/sys/arch/arm/dts/ |
| sun50i-a64.dtsi | 34 simple-audio-card,mclk-fs = <256>;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv730_dpm.c | 125 LPRV7XX_SMC_MCLK_VALUE mclk)
190 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
191 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
192 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock);
193 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
194 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
195 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
196 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss);
197 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
301 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl)
[all...] |
| radeon_rv740_dpm.c | 120 DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n");
193 RV7XX_SMC_MCLK_VALUE *mclk)
276 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
277 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
278 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
279 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
280 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
281 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
282 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl)
[all...] |
| radeon_rv770_dpm.c | 392 RV7XX_SMC_MCLK_VALUE *mclk)
477 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
478 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
479 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
480 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
481 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
482 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
483 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
596 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
607 if (mclk <= pi->mvdd_split_frequency)
2185 u32 sclk, mclk; local
[all...] |
| radeon_cypress_dpm.c | 429 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
436 if (mclk <= pi->mclk_strobe_mode_threshold)
438 result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
481 RV7XX_SMC_MCLK_VALUE *mclk,
603 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
604 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
605 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
606 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
607 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
608 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl)
[all...] |
| radeon_btc_dpm.c | 1249 u32 *sclk, u32 *mclk)
1253 if ((sclk == NULL) || (mclk == NULL))
1260 (btc_blacklist_clocks[i].mclk == *mclk))
1269 btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk);
1279 if ((pl->mclk == 0) || (pl->sclk == 0))
1282 if (pl->mclk == pl->sclk)
1285 if (pl->mclk > pl->sclk) {
1286 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
1289 (pl->mclk
2106 u32 mclk, sclk; local
[all...] |
| btc_dpm.h | 48 u32 *sclk, u32 *mclk);
|
| rv6xx_dpm.h | 83 u32 mclk; member in struct:rv6xx_pl
|
| rv770_dpm.h | 146 u32 mclk; member in struct:rv7xx_pl
187 LPRV7XX_SMC_MCLK_VALUE mclk);
208 RV7XX_SMC_MCLK_VALUE *mclk);
222 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
|
| radeon_ni_dpm.c | 797 u32 mclk; local
814 if (ps->performance_levels[i].mclk > max_limits->mclk)
815 ps->performance_levels[i].mclk = max_limits->mclk;
829 ps->performance_levels[0].mclk =
830 ps->performance_levels[ps->performance_level_count - 1].mclk;
835 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
837 &ps->performance_levels[0].mclk);
848 mclk = ps->performance_levels[0].mclk
[all...] |
| radeon_si_dpm.c | 2979 u32 mclk, sclk; local
3041 if (ps->performance_levels[i].mclk > max_limits->mclk)
3042 ps->performance_levels[i].mclk = max_limits->mclk;
3066 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3067 ps->performance_levels[i].mclk = max_mclk_vddci;
3070 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3071 ps->performance_levels[i].mclk = max_mclk_vddc;
3074 if (ps->performance_levels[i].mclk > max_mclk
6888 u32 sclk, mclk; local
[all...] |
| radeon_ci_dpm.c | 786 /* disable mclk switching if the refresh is >120Hz, even if the
806 u32 sclk, mclk; local
835 if (ps->performance_levels[i].mclk > max_limits->mclk)
836 ps->performance_levels[i].mclk = max_limits->mclk;
845 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
848 mclk = ps->performance_levels[0].mclk;
3869 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; local
3909 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; local
5626 u32 sclk, mclk; local
5955 u32 mclk = ci_get_average_mclk_freq(rdev); local
5991 u32 mclk = ci_get_average_mclk_freq(rdev); local
[all...] |
| radeon_rv6xx_dpm.c | 461 state->high.mclk;
463 state->high.mclk;
465 state->medium.mclk;
467 state->low.mclk;
471 if (state->high.mclk == state->medium.mclk)
478 if (state->medium.mclk == state->low.mclk)
1826 u32 sclk, mclk; local
1845 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow)
[all...] |
| cypress_dpm.h | 160 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);
|
| /src/sys/arch/mips/ingenic/ |
| apbus.c | 129 uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv; local
148 mclk = (48000 * (m + 1) / (n + 1)) / (p + 1);
152 pclk = mclk / pdiv;
154 cclk = mclk / cdiv;
156 aprint_debug_dev(self, "mclk %d kHz\n", mclk);
252 aa.aa_mclk = mclk;
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/allwinner/ |
| sun5i-gr8.dtsi | 106 i2s0_mclk_pin: i2s0-mclk-pin {
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| power_state.h | 180 unsigned long mclk; member in struct:pp_clock_engine_request
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 3297 if ((pl->mclk == 0) || (pl->sclk == 0))
3300 if (pl->mclk == pl->sclk)
3303 if (pl->mclk > pl->sclk) {
3304 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3307 (pl->mclk +
3311 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3312 pl->mclk = btc_get_valid_mclk(adev,
3313 max_limits->mclk,
3439 u32 mclk, sclk; local
3501 if (ps->performance_levels[i].mclk > max_limits->mclk
7295 u32 sclk, mclk; local
7997 uint32_t sclk, mclk; local
[all...] |
| amdgpu_dpm.h | 109 u32 mclk; member in struct:amdgpu_blacklist_clocks
115 u32 mclk; member in struct:amdgpu_clock_and_voltage_limits
155 u32 mclk; member in struct:amdgpu_phase_shedding_limits_entry
|
| amdgpu_atombios.h | 98 u32 mclk[MAX_AC_TIMING_ENTRIES]; member in struct:atom_memory_clock_range_table
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramgt215.c | 461 gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk)
463 ram_wr32(fuc, 0x004004, mclk->pll);
505 struct gt215_clk_info mclk; local
556 ret = gt215_pll_info(device->clk, 0x12, 0x4000, freq, &mclk);
558 nvkm_error(subdev, "failed mclk calculation\n");
607 pll2pll = (!(ctrl & 0x00000008)) && mclk.pll;
620 if (mclk.pll && !pll2pll) {
621 ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101);
622 gt215_ram_lock_pll(fuc, &mclk);
696 gt215_ram_lock_pll(fuc, &mclk);
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/ |
| imx6q-bx50v3.dtsi | 46 mclk: clock-mclk {
232 clocks = <&mclk>;
|
| /src/sys/external/bsd/drm2/dist/drm/ast/ |
| ast_main.c | 311 ast->mclk = 800;
313 ast->mclk = 396;
392 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
505 DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
506 ast->mclk, ast->dram_type,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_services_types.h | 66 struct dm_pp_clock_range mclk; member in struct:dm_pp_gpu_clock_range
208 /*Controller Index of primary display - used in MCLK SMC switching hang
211 /*htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
|
