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    Searched refs:mmCP_MEM_SLP_CNTL (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_mxgpu_vi.c 96 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
227 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
amdgpu_si.c 552 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
649 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
749 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
829 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
906 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
amdgpu_gfx_v6_0.c 2622 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2625 WREG32(mmCP_MEM_SLP_CNTL, data);
2646 data = RREG32(mmCP_MEM_SLP_CNTL);
2649 WREG32(mmCP_MEM_SLP_CNTL, data);
amdgpu_gfx_v8_0.c 312 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
475 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
682 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
715 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5492 data = RREG32(mmCP_MEM_SLP_CNTL);
5690 data = RREG32(mmCP_MEM_SLP_CNTL);
5693 WREG32(mmCP_MEM_SLP_CNTL, data);
amdgpu_gfx_v10_0.c 4068 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4071 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4092 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4095 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4300 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
amdgpu_gfx_v7_0.c 3631 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3634 WREG32(mmCP_MEM_SLP_CNTL, data);
3684 data = RREG32(mmCP_MEM_SLP_CNTL);
3687 WREG32(mmCP_MEM_SLP_CNTL, data);
amdgpu_gfx_v9_0.c 4547 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4550 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4576 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4579 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4830 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 457 #define mmCP_MEM_SLP_CNTL 0x3079
gfx_7_0_d.h 257 #define mmCP_MEM_SLP_CNTL 0x3079
gfx_7_2_d.h 259 #define mmCP_MEM_SLP_CNTL 0x3079
gfx_8_0_d.h 291 #define mmCP_MEM_SLP_CNTL 0x3079
gfx_8_1_d.h 291 #define mmCP_MEM_SLP_CNTL 0x3079
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2479 #define mmCP_MEM_SLP_CNTL 0x1079
gc_9_1_offset.h 2756 #define mmCP_MEM_SLP_CNTL 0x1079
gc_9_2_1_offset.h 2694 #define mmCP_MEM_SLP_CNTL 0x1079
gc_10_1_0_offset.h 4820 #define mmCP_MEM_SLP_CNTL 0x1e19
    [all...]

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