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    Searched refs:mmCP_PFP_UCODE_ADDR (Results 1 - 17 of 17) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_ci_baco.c 163 { CMD_WRITE, mmCP_PFP_UCODE_ADDR, 0, 0, 0, 0 }
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_psp_v10_0.c 264 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
amdgpu_psp_v12_0.c 368 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
amdgpu_psp_v3_1.c 444 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
amdgpu_psp_v11_0.c 597 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
amdgpu_gfx_v6_0.c 1999 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2002 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2022 WREG32(mmCP_PFP_UCODE_ADDR, 0);
amdgpu_gfx_v7_0.c 2494 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2497 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
amdgpu_gfx_v9_0.c 3086 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
3089 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 490 #define mmCP_PFP_UCODE_ADDR 0x3054
gfx_7_0_d.h 242 #define mmCP_PFP_UCODE_ADDR 0x3054
gfx_7_2_d.h 244 #define mmCP_PFP_UCODE_ADDR 0x3054
gfx_8_0_d.h 273 #define mmCP_PFP_UCODE_ADDR 0xf814
gfx_8_1_d.h 274 #define mmCP_PFP_UCODE_ADDR 0xf814
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6714 #define mmCP_PFP_UCODE_ADDR 0x5814
gc_9_1_offset.h 6938 #define mmCP_PFP_UCODE_ADDR 0x5814
gc_9_2_1_offset.h 6966 #define mmCP_PFP_UCODE_ADDR 0x5814
gc_10_1_0_offset.h     [all...]

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