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    Searched refs:mmCP_RB0_CNTL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 2120 WREG32(mmCP_RB0_CNTL, tmp);
2123 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2135 WREG32(mmCP_RB0_CNTL, tmp);
amdgpu_gfx_v7_0.c 2635 WREG32(mmCP_RB0_CNTL, tmp);
2638 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2651 WREG32(mmCP_RB0_CNTL, tmp);
amdgpu_gfx_v8_0.c 4289 WREG32(mmCP_RB0_CNTL, tmp);
4292 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4305 WREG32(mmCP_RB0_CNTL, tmp);
amdgpu_gfx_v10_0.c 2796 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2816 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
amdgpu_gfx_v9_0.c 3197 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
3214 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 497 #define mmCP_RB0_CNTL 0x3041
gfx_7_0_d.h 203 #define mmCP_RB0_CNTL 0x3041
gfx_7_2_d.h 203 #define mmCP_RB0_CNTL 0x3041
gfx_8_0_d.h 227 #define mmCP_RB0_CNTL 0x3041
gfx_8_1_d.h 228 #define mmCP_RB0_CNTL 0x3041
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 56 { 0x0840800a, mmCP_RB0_CNTL },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2363 #define mmCP_RB0_CNTL 0x1041
gc_9_1_offset.h 2640 #define mmCP_RB0_CNTL 0x1041
gc_9_2_1_offset.h 2578 #define mmCP_RB0_CNTL 0x1041
gc_10_1_0_offset.h 4710 #define mmCP_RB0_CNTL 0x1de1
    [all...]

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