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    Searched refs:mmCP_RB0_WPTR (Results 1 - 14 of 14) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 2125 WREG32(mmCP_RB0_WPTR, ring->wptr);
2158 return RREG32(mmCP_RB0_WPTR);
2171 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2172 (void)RREG32(mmCP_RB0_WPTR);
amdgpu_gfx_v7_0.c 2640 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2675 return RREG32(mmCP_RB0_WPTR);
2682 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2683 (void)RREG32(mmCP_RB0_WPTR);
amdgpu_gfx_v10_0.c 2800 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4328 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4344 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
amdgpu_gfx_v8_0.c 4294 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6026 return RREG32(mmCP_RB0_WPTR);
6038 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6039 (void)RREG32(mmCP_RB0_WPTR);
amdgpu_gfx_v9_0.c 3201 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4860 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4876 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 501 #define mmCP_RB0_WPTR 0x3045
gfx_7_0_d.h 216 #define mmCP_RB0_WPTR 0x3045
gfx_7_2_d.h 216 #define mmCP_RB0_WPTR 0x3045
gfx_8_0_d.h 240 #define mmCP_RB0_WPTR 0x3045
gfx_8_1_d.h 241 #define mmCP_RB0_WPTR 0x3045
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2417 #define mmCP_RB0_WPTR 0x1054
gc_9_1_offset.h 2694 #define mmCP_RB0_WPTR 0x1054
gc_9_2_1_offset.h 2632 #define mmCP_RB0_WPTR 0x1054
gc_10_1_0_offset.h 4760 #define mmCP_RB0_WPTR 0x1df4
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