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    Searched refs:mmCP_RB1_BASE (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 502 #define mmCP_RB1_BASE 0x3060
gfx_7_0_d.h 200 #define mmCP_RB1_BASE 0x3060
gfx_7_2_d.h 200 #define mmCP_RB1_BASE 0x3060
gfx_8_0_d.h 224 #define mmCP_RB1_BASE 0x3060
gfx_8_1_d.h 225 #define mmCP_RB1_BASE 0x3060
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 2220 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
amdgpu_gfx_v10_0.c 2854 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2445 #define mmCP_RB1_BASE 0x1060
gc_9_1_offset.h 2722 #define mmCP_RB1_BASE 0x1060
gc_9_2_1_offset.h 2660 #define mmCP_RB1_BASE 0x1060
gc_10_1_0_offset.h 4788 #define mmCP_RB1_BASE 0x1e00
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