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Searched refs:mmCP_RB1_WPTR (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c	`2160 return RREG32(mmCP_RB1_WPTR); 2180 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2181 (void)RREG32(mmCP_RB1_WPTR); 2212 WREG32(mmCP_RB1_WPTR, ring->wptr);`
amdgpu_gfx_v10_0.c	`2837 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h	`507 #define mmCP_RB1_WPTR 0x3064`
gfx_7_0_d.h	`218 #define mmCP_RB1_WPTR 0x3064`
gfx_7_2_d.h	`218 #define mmCP_RB1_WPTR 0x3064`
gfx_8_0_d.h	`242 #define mmCP_RB1_WPTR 0x3064`
gfx_8_1_d.h	`243 #define mmCP_RB1_WPTR 0x3064`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2425 #define mmCP_RB1_WPTR 0x1056`
gc_9_1_offset.h	`2702 #define mmCP_RB1_WPTR 0x1056`
gc_9_2_1_offset.h	`2640 #define mmCP_RB1_WPTR 0x1056`
gc_10_1_0_offset.h	`4768 #define mmCP_RB1_WPTR 0x1df6 [all...]`

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