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    Searched refs:mmCRTC_CONTROL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_resource.c 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
121 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
125 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
129 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
133 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_resource.c 124 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
128 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
132 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
136 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
140 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
amdgpu_dce110_timing_generator_v.c 600 uint32_t address = mmCRTC_CONTROL;
amdgpu_dce110_timing_generator.c 116 uint32_t address = CRTC_REG(mmCRTC_CONTROL);
2102 addr = CRTC_REG(mmCRTC_CONTROL);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 123 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
127 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
131 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
135 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
139 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_resource.c 118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
124 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
130 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
136 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
142 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
148 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 425 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
496 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
500 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
502 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
amdgpu_dce_v11_0.c 441 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
522 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
526 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
528 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
amdgpu_dce_v8_0.c 359 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
436 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
440 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
442 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
amdgpu_dce_v6_0.c 392 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
396 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
398 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 966 #define mmCRTC_CONTROL 0x1B9C
dce_8_0_d.h 335 #define mmCRTC_CONTROL 0x1b9c
dce_10_0_d.h 390 #define mmCRTC_CONTROL 0x1b9c
dce_11_0_d.h 317 #define mmCRTC_CONTROL 0x1b9c
dce_11_2_d.h 324 #define mmCRTC_CONTROL 0x1b9c

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