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    Searched refs:mmD3VGA_CONTROL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 406 offset = mmD3VGA_CONTROL - mmD1VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 1823 addr = mmD3VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1820 mmD3VGA_CONTROL,
amdgpu_dce_v11_0.c 1862 mmD3VGA_CONTROL,
amdgpu_dce_v6_0.c 1786 mmD3VGA_CONTROL,
amdgpu_dce_v8_0.c 1749 mmD3VGA_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 1045 #define mmD3VGA_CONTROL 0x00F8
dce_8_0_d.h 5148 #define mmD3VGA_CONTROL 0xf8
dce_10_0_d.h 6031 #define mmD3VGA_CONTROL 0xf8
dce_11_0_d.h 6108 #define mmD3VGA_CONTROL 0xf8
dce_11_2_d.h 7782 #define mmD3VGA_CONTROL 0xf8
dce_12_0_offset.h 642 #define mmD3VGA_CONTROL 0x0038
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h 452 #define mmD3VGA_CONTROL 0x0038
    [all...]
dcn_2_1_0_offset.h 140 #define mmD3VGA_CONTROL 0x0038
    [all...]
dcn_2_0_0_offset.h 120 #define mmD3VGA_CONTROL 0x0038
    [all...]

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