HomeSort by: relevance | last modified time | path
    Searched refs:mmD5VGA_CONTROL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 412 offset = mmD5VGA_CONTROL - mmD1VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 1829 addr = mmD5VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1822 mmD5VGA_CONTROL,
amdgpu_dce_v11_0.c 1864 mmD5VGA_CONTROL,
amdgpu_dce_v6_0.c 1788 mmD5VGA_CONTROL,
amdgpu_dce_v8_0.c 1751 mmD5VGA_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 1047 #define mmD5VGA_CONTROL 0x00FA
dce_8_0_d.h 5150 #define mmD5VGA_CONTROL 0xfa
dce_10_0_d.h 6033 #define mmD5VGA_CONTROL 0xfa
dce_11_0_d.h 6110 #define mmD5VGA_CONTROL 0xfa
dce_11_2_d.h 7784 #define mmD5VGA_CONTROL 0xfa
dce_12_0_offset.h 646 #define mmD5VGA_CONTROL 0x003a
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h 456 #define mmD5VGA_CONTROL 0x003a
    [all...]
dcn_2_1_0_offset.h 144 #define mmD5VGA_CONTROL 0x003a
    [all...]
dcn_2_0_0_offset.h 124 #define mmD5VGA_CONTROL 0x003a
    [all...]

Completed in 316 milliseconds