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    Searched refs:mmD6VGA_CONTROL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 415 offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 1832 addr = mmD6VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1823 mmD6VGA_CONTROL,
amdgpu_dce_v11_0.c 1865 mmD6VGA_CONTROL,
amdgpu_dce_v6_0.c 1789 mmD6VGA_CONTROL,
amdgpu_dce_v8_0.c 1752 mmD6VGA_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 1048 #define mmD6VGA_CONTROL 0x00FB
dce_8_0_d.h 5151 #define mmD6VGA_CONTROL 0xfb
dce_10_0_d.h 6034 #define mmD6VGA_CONTROL 0xfb
dce_11_0_d.h 6111 #define mmD6VGA_CONTROL 0xfb
dce_11_2_d.h 7785 #define mmD6VGA_CONTROL 0xfb
dce_12_0_offset.h 648 #define mmD6VGA_CONTROL 0x003b
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h 458 #define mmD6VGA_CONTROL 0x003b
    [all...]
dcn_2_1_0_offset.h 146 #define mmD6VGA_CONTROL 0x003b
    [all...]
dcn_2_0_0_offset.h 126 #define mmD6VGA_CONTROL 0x003b
    [all...]

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