HomeSort by: relevance | last modified time | path
    Searched refs:mmDC_HPD_INT_CONTROL (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 318 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
323 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
355 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
357 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
3047 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3049 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3052 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3054 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3197 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3199 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)
    [all...]
amdgpu_dce_v11_0.c 336 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
341 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
373 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
375 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
3173 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3175 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3178 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3180 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_10_0_d.h 7098 #define mmDC_HPD_INT_CONTROL 0x1899
dce_11_0_d.h 7283 #define mmDC_HPD_INT_CONTROL 0x1899
dce_11_2_d.h 8665 #define mmDC_HPD_INT_CONTROL 0x1899

Completed in 76 milliseconds