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Searched refs:mmDPG_WATERMARK_MASK_CONTROL (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_resource.c	`121 - mmDPG_WATERMARK_MASK_CONTROL), 127 - mmDPG_WATERMARK_MASK_CONTROL), 133 - mmDPG_WATERMARK_MASK_CONTROL), 139 - mmDPG_WATERMARK_MASK_CONTROL), 145 - mmDPG_WATERMARK_MASK_CONTROL), 151 - mmDPG_WATERMARK_MASK_CONTROL),`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v8_0.c	`1065 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1069 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1074 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1077 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1082 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);`
amdgpu_dce_v10_0.c	`1130 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1132 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1139 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1145 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);`
amdgpu_dce_v11_0.c	`1156 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1158 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1165 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1171 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_8_0_d.h	`5182 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32`
dce_10_0_d.h	`6395 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32`
dce_11_0_d.h	`6518 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32`
dce_11_2_d.h	`7816 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32`

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