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    Searched refs:mmHDMI_ACR_44_0 (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1504 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1506 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
amdgpu_dce_v11_0.c 1546 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1548 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
amdgpu_dce_v6_0.c 1435 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1437 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
amdgpu_dce_v8_0.c 1463 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 3854 #define mmHDMI_ACR_44_0 0x1C39
dce_8_0_d.h 3201 #define mmHDMI_ACR_44_0 0x1c39
dce_10_0_d.h 3980 #define mmHDMI_ACR_44_0 0x4a30
dce_11_0_d.h 3849 #define mmHDMI_ACR_44_0 0x4a30
dce_11_2_d.h 5080 #define mmHDMI_ACR_44_0 0x4a30

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