HomeSort by: relevance | last modified time | path
    Searched refs:mmHDMI_ACR_48_0 (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1511 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1513 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
amdgpu_dce_v11_0.c 1553 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1555 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
amdgpu_dce_v6_0.c 1442 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1444 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
amdgpu_dce_v8_0.c 1466 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 3856 #define mmHDMI_ACR_48_0 0x1C3B
dce_8_0_d.h 3217 #define mmHDMI_ACR_48_0 0x1c3b
dce_10_0_d.h 3996 #define mmHDMI_ACR_48_0 0x4a32
dce_11_0_d.h 3869 #define mmHDMI_ACR_48_0 0x4a32
dce_11_2_d.h 5100 #define mmHDMI_ACR_48_0 0x4a32

Completed in 103 milliseconds