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Searched refs:mmHDMI_INFOFRAME_CONTROL0 (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c	`1645 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1650 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1729 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1734 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);`
amdgpu_dce_v11_0.c	`1687 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1692 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1771 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1776 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);`
amdgpu_dce_v6_0.c	`1593 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1598 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1608 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1613 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);`
amdgpu_dce_v8_0.c	`1594 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, 1663 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h	`3866 #define mmHDMI_INFOFRAME_CONTROL0 0x1C11`
dce_8_0_d.h	`2937 #define mmHDMI_INFOFRAME_CONTROL0 0x1c11`
dce_10_0_d.h	`3716 #define mmHDMI_INFOFRAME_CONTROL0 0x4a0e`
dce_11_0_d.h	`3519 #define mmHDMI_INFOFRAME_CONTROL0 0x4a0e`
dce_11_2_d.h	`4750 #define mmHDMI_INFOFRAME_CONTROL0 0x4a0e`

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