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    Searched refs:mmHDMI_INFOFRAME_CONTROL1 (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1657 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1660 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1736 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1738 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
amdgpu_dce_v11_0.c 1699 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1702 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1778 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1780 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
amdgpu_dce_v6_0.c 1486 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1490 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1600 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1602 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
amdgpu_dce_v8_0.c 1601 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1667 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 3867 #define mmHDMI_INFOFRAME_CONTROL1 0x1C12
dce_8_0_d.h 2945 #define mmHDMI_INFOFRAME_CONTROL1 0x1c12
dce_10_0_d.h 3724 #define mmHDMI_INFOFRAME_CONTROL1 0x4a0f
dce_11_0_d.h 3529 #define mmHDMI_INFOFRAME_CONTROL1 0x4a0f
dce_11_2_d.h 4760 #define mmHDMI_INFOFRAME_CONTROL1 0x4a0f

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