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Searched refs:mmIH_RB_CNTL (Results 1 - 14 of 14) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_ih.c	`68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 73 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 91 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 144 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 208 tmp = RREG32(mmIH_RB_CNTL); 210 WREG32(mmIH_RB_CNTL, tmp);`
amdgpu_cz_ih.c	`68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 73 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 91 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 146 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 210 tmp = RREG32(mmIH_RB_CNTL); 212 WREG32(mmIH_RB_CNTL, tmp);`
amdgpu_iceland_ih.c	`68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 73 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 91 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 146 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 210 tmp = RREG32(mmIH_RB_CNTL); 212 WREG32(mmIH_RB_CNTL, tmp);`
amdgpu_tonga_ih.c	`67 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 71 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 84 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 88 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 140 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 212 tmp = RREG32(mmIH_RB_CNTL); 214 WREG32(mmIH_RB_CNTL, tmp);`
amdgpu_navi10_ih.c	`52 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 56 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 69 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 73 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 130 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 144 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 240 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);`
amdgpu_vega10_ih.c	`54 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 64 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 110 u32 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 241 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL); 251 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); 418 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_1_0_d.h	`233 #define mmIH_RB_CNTL 0x0F80`
osssys_4_0_1_offset.h	`122 #define mmIH_RB_CNTL 0x0080`
osssys_4_0_offset.h	`122 #define mmIH_RB_CNTL 0x0080`
osssys_5_0_0_offset.h	`122 #define mmIH_RB_CNTL 0x0080`
oss_2_4_d.h	`45 #define mmIH_RB_CNTL 0xe30`
oss_2_0_d.h	`45 #define mmIH_RB_CNTL 0xf80`
oss_3_0_1_d.h	`45 #define mmIH_RB_CNTL 0xe30`
oss_3_0_d.h	`45 #define mmIH_RB_CNTL 0xe30`

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