1 /* $NetBSD: amdgpu_cik_ih.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_cik_ih.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $"); 28 29 #include <linux/pci.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_ih.h" 33 #include "cikd.h" 34 35 #include "bif/bif_4_1_d.h" 36 #include "bif/bif_4_1_sh_mask.h" 37 38 #include "oss/oss_2_0_d.h" 39 #include "oss/oss_2_0_sh_mask.h" 40 41 /* 42 * Interrupts 43 * Starting with r6xx, interrupts are handled via a ring buffer. 44 * Ring buffers are areas of GPU accessible memory that the GPU 45 * writes interrupt vectors into and the host reads vectors out of. 46 * There is a rptr (read pointer) that determines where the 47 * host is currently reading, and a wptr (write pointer) 48 * which determines where the GPU has written. When the 49 * pointers are equal, the ring is idle. When the GPU 50 * writes vectors to the ring buffer, it increments the 51 * wptr. When there is an interrupt, the host then starts 52 * fetching commands and processing them until the pointers are 53 * equal again at which point it updates the rptr. 54 */ 55 56 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev); 57 58 /** 59 * cik_ih_enable_interrupts - Enable the interrupt ring buffer 60 * 61 * @adev: amdgpu_device pointer 62 * 63 * Enable the interrupt ring buffer (CIK). 64 */ 65 static void cik_ih_enable_interrupts(struct amdgpu_device *adev) 66 { 67 u32 ih_cntl = RREG32(mmIH_CNTL); 68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 69 70 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK; 71 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK; 72 WREG32(mmIH_CNTL, ih_cntl); 73 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 74 adev->irq.ih.enabled = true; 75 } 76 77 /** 78 * cik_ih_disable_interrupts - Disable the interrupt ring buffer 79 * 80 * @adev: amdgpu_device pointer 81 * 82 * Disable the interrupt ring buffer (CIK). 83 */ 84 static void cik_ih_disable_interrupts(struct amdgpu_device *adev) 85 { 86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 87 u32 ih_cntl = RREG32(mmIH_CNTL); 88 89 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK; 90 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK; 91 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 92 WREG32(mmIH_CNTL, ih_cntl); 93 /* set rptr, wptr to 0 */ 94 WREG32(mmIH_RB_RPTR, 0); 95 WREG32(mmIH_RB_WPTR, 0); 96 adev->irq.ih.enabled = false; 97 adev->irq.ih.rptr = 0; 98 } 99 100 /** 101 * cik_ih_irq_init - init and enable the interrupt ring 102 * 103 * @adev: amdgpu_device pointer 104 * 105 * Allocate a ring buffer for the interrupt controller, 106 * enable the RLC, disable interrupts, enable the IH 107 * ring buffer and enable it (CIK). 108 * Called at device load and reume. 109 * Returns 0 for success, errors for failure. 110 */ 111 static int cik_ih_irq_init(struct amdgpu_device *adev) 112 { 113 struct amdgpu_ih_ring *ih = &adev->irq.ih; 114 int rb_bufsz; 115 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 116 117 /* disable irqs */ 118 cik_ih_disable_interrupts(adev); 119 120 /* setup interrupt control */ 121 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 122 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 123 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 124 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 125 */ 126 interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK; 127 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 128 interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK; 129 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 130 131 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 132 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 133 134 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK | 135 IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK | 136 (rb_bufsz << 1)); 137 138 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; 139 140 /* set the writeback address whether it's enabled or not */ 141 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 142 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 143 144 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 145 146 /* set rptr, wptr to 0 */ 147 WREG32(mmIH_RB_RPTR, 0); 148 WREG32(mmIH_RB_WPTR, 0); 149 150 /* Default settings for IH_CNTL (disabled at first) */ 151 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) | 152 (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) | 153 (0 << IH_CNTL__MC_VMID__SHIFT); 154 /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */ 155 if (adev->irq.msi_enabled) 156 ih_cntl |= IH_CNTL__RPTR_REARM_MASK; 157 WREG32(mmIH_CNTL, ih_cntl); 158 159 pci_set_master(adev->pdev); 160 161 /* enable irqs */ 162 cik_ih_enable_interrupts(adev); 163 164 return 0; 165 } 166 167 /** 168 * cik_ih_irq_disable - disable interrupts 169 * 170 * @adev: amdgpu_device pointer 171 * 172 * Disable interrupts on the hw (CIK). 173 */ 174 static void cik_ih_irq_disable(struct amdgpu_device *adev) 175 { 176 cik_ih_disable_interrupts(adev); 177 /* Wait and acknowledge irq */ 178 mdelay(1); 179 } 180 181 /** 182 * cik_ih_get_wptr - get the IH ring buffer wptr 183 * 184 * @adev: amdgpu_device pointer 185 * 186 * Get the IH ring buffer wptr from either the register 187 * or the writeback memory buffer (CIK). Also check for 188 * ring buffer overflow and deal with it. 189 * Used by cik_irq_process(). 190 * Returns the value of the wptr. 191 */ 192 static u32 cik_ih_get_wptr(struct amdgpu_device *adev, 193 struct amdgpu_ih_ring *ih) 194 { 195 u32 wptr, tmp; 196 197 wptr = le32_to_cpu(*ih->wptr_cpu); 198 199 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { 200 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; 201 /* When a ring buffer overflow happen start parsing interrupt 202 * from the last not overwritten vector (wptr + 16). Hopefully 203 * this should allow us to catchup. 204 */ 205 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 206 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 207 ih->rptr = (wptr + 16) & ih->ptr_mask; 208 tmp = RREG32(mmIH_RB_CNTL); 209 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 210 WREG32(mmIH_RB_CNTL, tmp); 211 } 212 return (wptr & ih->ptr_mask); 213 } 214 215 /* CIK IV Ring 216 * Each IV ring entry is 128 bits: 217 * [7:0] - interrupt source id 218 * [31:8] - reserved 219 * [59:32] - interrupt source data 220 * [63:60] - reserved 221 * [71:64] - RINGID 222 * CP: 223 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0] 224 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher 225 * - for gfx, hw shader state (0=PS...5=LS, 6=CS) 226 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes 227 * PIPE_ID - ME0 0=3D 228 * - ME1&2 compute dispatcher (4 pipes each) 229 * SDMA: 230 * INSTANCE_ID [1:0], QUEUE_ID[1:0] 231 * INSTANCE_ID - 0 = sdma0, 1 = sdma1 232 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1 233 * [79:72] - VMID 234 * [95:80] - PASID 235 * [127:96] - reserved 236 */ 237 238 /** 239 * cik_ih_decode_iv - decode an interrupt vector 240 * 241 * @adev: amdgpu_device pointer 242 * 243 * Decodes the interrupt vector at the current rptr 244 * position and also advance the position. 245 */ 246 static void cik_ih_decode_iv(struct amdgpu_device *adev, 247 struct amdgpu_ih_ring *ih, 248 struct amdgpu_iv_entry *entry) 249 { 250 /* wptr/rptr are in bytes! */ 251 u32 ring_index = ih->rptr >> 2; 252 uint32_t dw[4]; 253 254 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 255 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 256 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 257 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 258 259 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 260 entry->src_id = dw[0] & 0xff; 261 entry->src_data[0] = dw[1] & 0xfffffff; 262 entry->ring_id = dw[2] & 0xff; 263 entry->vmid = (dw[2] >> 8) & 0xff; 264 entry->pasid = (dw[2] >> 16) & 0xffff; 265 266 /* wptr/rptr are in bytes! */ 267 ih->rptr += 16; 268 } 269 270 /** 271 * cik_ih_set_rptr - set the IH ring buffer rptr 272 * 273 * @adev: amdgpu_device pointer 274 * 275 * Set the IH ring buffer rptr. 276 */ 277 static void cik_ih_set_rptr(struct amdgpu_device *adev, 278 struct amdgpu_ih_ring *ih) 279 { 280 WREG32(mmIH_RB_RPTR, ih->rptr); 281 } 282 283 static int cik_ih_early_init(void *handle) 284 { 285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 286 int ret; 287 288 ret = amdgpu_irq_add_domain(adev); 289 if (ret) 290 return ret; 291 292 cik_ih_set_interrupt_funcs(adev); 293 294 return 0; 295 } 296 297 static int cik_ih_sw_init(void *handle) 298 { 299 int r; 300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 301 302 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); 303 if (r) 304 return r; 305 306 r = amdgpu_irq_init(adev); 307 308 return r; 309 } 310 311 static int cik_ih_sw_fini(void *handle) 312 { 313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 314 315 amdgpu_irq_fini(adev); 316 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 317 amdgpu_irq_remove_domain(adev); 318 319 return 0; 320 } 321 322 static int cik_ih_hw_init(void *handle) 323 { 324 int r; 325 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 326 327 r = cik_ih_irq_init(adev); 328 if (r) 329 return r; 330 331 return 0; 332 } 333 334 static int cik_ih_hw_fini(void *handle) 335 { 336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 337 338 cik_ih_irq_disable(adev); 339 340 return 0; 341 } 342 343 static int cik_ih_suspend(void *handle) 344 { 345 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 346 347 return cik_ih_hw_fini(adev); 348 } 349 350 static int cik_ih_resume(void *handle) 351 { 352 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 353 354 return cik_ih_hw_init(adev); 355 } 356 357 static bool cik_ih_is_idle(void *handle) 358 { 359 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 360 u32 tmp = RREG32(mmSRBM_STATUS); 361 362 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 363 return false; 364 365 return true; 366 } 367 368 static int cik_ih_wait_for_idle(void *handle) 369 { 370 unsigned i; 371 u32 tmp; 372 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 373 374 for (i = 0; i < adev->usec_timeout; i++) { 375 /* read MC_STATUS */ 376 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; 377 if (!tmp) 378 return 0; 379 udelay(1); 380 } 381 return -ETIMEDOUT; 382 } 383 384 static int cik_ih_soft_reset(void *handle) 385 { 386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 387 388 u32 srbm_soft_reset = 0; 389 u32 tmp = RREG32(mmSRBM_STATUS); 390 391 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 392 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 393 394 if (srbm_soft_reset) { 395 tmp = RREG32(mmSRBM_SOFT_RESET); 396 tmp |= srbm_soft_reset; 397 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 398 WREG32(mmSRBM_SOFT_RESET, tmp); 399 tmp = RREG32(mmSRBM_SOFT_RESET); 400 401 udelay(50); 402 403 tmp &= ~srbm_soft_reset; 404 WREG32(mmSRBM_SOFT_RESET, tmp); 405 tmp = RREG32(mmSRBM_SOFT_RESET); 406 407 /* Wait a little for things to settle down */ 408 udelay(50); 409 } 410 411 return 0; 412 } 413 414 static int cik_ih_set_clockgating_state(void *handle, 415 enum amd_clockgating_state state) 416 { 417 return 0; 418 } 419 420 static int cik_ih_set_powergating_state(void *handle, 421 enum amd_powergating_state state) 422 { 423 return 0; 424 } 425 426 static const struct amd_ip_funcs cik_ih_ip_funcs = { 427 .name = "cik_ih", 428 .early_init = cik_ih_early_init, 429 .late_init = NULL, 430 .sw_init = cik_ih_sw_init, 431 .sw_fini = cik_ih_sw_fini, 432 .hw_init = cik_ih_hw_init, 433 .hw_fini = cik_ih_hw_fini, 434 .suspend = cik_ih_suspend, 435 .resume = cik_ih_resume, 436 .is_idle = cik_ih_is_idle, 437 .wait_for_idle = cik_ih_wait_for_idle, 438 .soft_reset = cik_ih_soft_reset, 439 .set_clockgating_state = cik_ih_set_clockgating_state, 440 .set_powergating_state = cik_ih_set_powergating_state, 441 }; 442 443 static const struct amdgpu_ih_funcs cik_ih_funcs = { 444 .get_wptr = cik_ih_get_wptr, 445 .decode_iv = cik_ih_decode_iv, 446 .set_rptr = cik_ih_set_rptr 447 }; 448 449 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev) 450 { 451 adev->irq.ih_funcs = &cik_ih_funcs; 452 } 453 454 const struct amdgpu_ip_block_version cik_ih_ip_block = 455 { 456 .type = AMD_IP_BLOCK_TYPE_IH, 457 .major = 2, 458 .minor = 0, 459 .rev = 0, 460 .funcs = &cik_ih_ip_funcs, 461 }; 462
Indexes created Sat Sep 20 22:09:52 GMT 2025