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Searched refs:mmIH_RB_RPTR (Results 1 - 14 of 14) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_ih.c	`94 WREG32(mmIH_RB_RPTR, 0); 147 WREG32(mmIH_RB_RPTR, 0); 280 WREG32(mmIH_RB_RPTR, ih->rptr);`
amdgpu_cz_ih.c	`94 WREG32(mmIH_RB_RPTR, 0); 149 WREG32(mmIH_RB_RPTR, 0); 259 WREG32(mmIH_RB_RPTR, ih->rptr);`
amdgpu_iceland_ih.c	`94 WREG32(mmIH_RB_RPTR, 0); 149 WREG32(mmIH_RB_RPTR, 0); 259 WREG32(mmIH_RB_RPTR, ih->rptr);`
amdgpu_tonga_ih.c	`90 WREG32(mmIH_RB_RPTR, 0); 147 WREG32(mmIH_RB_RPTR, 0); 266 WREG32(mmIH_RB_RPTR, ih->rptr);`
amdgpu_navi10_ih.c	`75 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 153 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 306 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);`
amdgpu_vega10_ih.c	`124 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 276 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); 491 reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); 527 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_1_0_d.h	`234 #define mmIH_RB_RPTR 0x0F82`
osssys_4_0_1_offset.h	`128 #define mmIH_RB_RPTR 0x0083`
osssys_4_0_offset.h	`128 #define mmIH_RB_RPTR 0x0083`
osssys_5_0_0_offset.h	`128 #define mmIH_RB_RPTR 0x0083`
oss_2_4_d.h	`47 #define mmIH_RB_RPTR 0xe32`
oss_2_0_d.h	`47 #define mmIH_RB_RPTR 0xf82`
oss_3_0_1_d.h	`47 #define mmIH_RB_RPTR 0xe32`
oss_3_0_d.h	`47 #define mmIH_RB_RPTR 0xe32`

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