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Searched refs:mmINPUT_CSC_CONTROL (Results 1 - 9 of 9) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c	`2126 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2129 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);`
amdgpu_dce_v11_0.c	`2168 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2170 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);`
amdgpu_dce_v6_0.c	`2062 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,`
amdgpu_dce_v8_0.c	`2032 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h	`3876 #define mmINPUT_CSC_CONTROL 0x1A35`
dce_8_0_d.h	`1901 #define mmINPUT_CSC_CONTROL 0x1a35`
dce_10_0_d.h	`2750 #define mmINPUT_CSC_CONTROL 0x1a35`
dce_11_0_d.h	`2504 #define mmINPUT_CSC_CONTROL 0x1a35`
dce_11_2_d.h	`3735 #define mmINPUT_CSC_CONTROL 0x1a35`

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