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    Searched refs:mmMC_VM_MX_L1_TLB_CNTL (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c 129 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
142 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
315 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
321 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
amdgpu_mmhub_v1_0.c 146 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
159 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
349 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
355 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
amdgpu_gmc_v7_0.c 639 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
645 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
760 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
764 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
amdgpu_gmc_v8_0.c 860 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
866 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
998 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
1002 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
amdgpu_gmc_v6_0.c 505 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
617 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_7_0_d.h 259 #define mmMC_VM_MX_L1_TLB_CNTL 0x819
gmc_8_2_d.h 296 #define mmMC_VM_MX_L1_TLB_CNTL 0x819
gmc_6_0_d.h 1053 #define mmMC_VM_MX_L1_TLB_CNTL 0x0819
gmc_7_1_d.h 290 #define mmMC_VM_MX_L1_TLB_CNTL 0x819
gmc_8_1_d.h 299 #define mmMC_VM_MX_L1_TLB_CNTL 0x819
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
mmhub_1_0_offset.h 1948 #define mmMC_VM_MX_L1_TLB_CNTL 0x0833
mmhub_9_1_offset.h 1980 #define mmMC_VM_MX_L1_TLB_CNTL 0x0833
mmhub_9_3_0_offset.h 1972 #define mmMC_VM_MX_L1_TLB_CNTL 0x0833
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 1695 #define mmMC_VM_MX_L1_TLB_CNTL 0x0987
gc_9_1_offset.h 1714 #define mmMC_VM_MX_L1_TLB_CNTL 0x0987
gc_9_2_1_offset.h 1656 #define mmMC_VM_MX_L1_TLB_CNTL 0x0987

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