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    Searched refs:mmRLC_AUTO_PG_CTRL (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v7_0.c 3797 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3800 WREG32(mmRLC_AUTO_PG_CTRL, data);
3807 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3810 WREG32(mmRLC_AUTO_PG_CTRL, data);
3930 data = RREG32(mmRLC_AUTO_PG_CTRL);
3933 WREG32(mmRLC_AUTO_PG_CTRL, data);
amdgpu_gfx_v6_0.c 2836 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2840 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
amdgpu_gfx_v9_0.c 2787 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2792 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1133 #define mmRLC_AUTO_PG_CTRL 0x310D
gfx_7_0_d.h 1295 #define mmRLC_AUTO_PG_CTRL 0x3115
gfx_7_2_d.h 1308 #define mmRLC_AUTO_PG_CTRL 0x3115
gfx_8_0_d.h 1408 #define mmRLC_AUTO_PG_CTRL 0xec55
gfx_8_1_d.h 1408 #define mmRLC_AUTO_PG_CTRL 0xec55
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6066 #define mmRLC_AUTO_PG_CTRL 0x4c55
gc_9_1_offset.h 6288 #define mmRLC_AUTO_PG_CTRL 0x4c55
gc_9_2_1_offset.h 6264 #define mmRLC_AUTO_PG_CTRL 0x4c55
gc_10_1_0_offset.h 9388 #define mmRLC_AUTO_PG_CTRL 0x4c55
    [all...]

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