| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_mxgpu_vi.c | 86 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
217 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
247 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
|
| amdgpu_gfx_v8_0.c | 213 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
311 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
325 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
356 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
388 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
430 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
474 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
488 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
575 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
585 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c
[all...] |
| amdgpu_si.c | 539 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
638 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
736 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
816 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
896 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
|
| amdgpu_gfx_v10_0.c | 1908 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4160 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4167 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4176 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4181 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4286 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
|
| amdgpu_gfx_v7_0.c | 3542 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3543 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3585 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3606 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3618 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
|
| amdgpu_gfx_v9_0.c | 3008 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4657 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4669 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4678 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4683 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4816 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
|
| amdgpu_gfx_v6_0.c | 2575 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2606 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_6_0_d.h | 1135 #define mmRLC_CGCG_CGLS_CTRL 0x3101
|
| gfx_7_0_d.h | 1283 #define mmRLC_CGCG_CGLS_CTRL 0x3109
|
| gfx_7_2_d.h | 1296 #define mmRLC_CGCG_CGLS_CTRL 0x3109
|
| gfx_8_0_d.h | 1394 #define mmRLC_CGCG_CGLS_CTRL 0xec49
|
| gfx_8_1_d.h | 1396 #define mmRLC_CGCG_CGLS_CTRL 0xec49
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| gc_9_0_offset.h | 6042 #define mmRLC_CGCG_CGLS_CTRL 0x4c49
|
| gc_9_1_offset.h | 6264 #define mmRLC_CGCG_CGLS_CTRL 0x4c49
|
| gc_9_2_1_offset.h | 6240 #define mmRLC_CGCG_CGLS_CTRL 0x4c49
|
| gc_10_1_0_offset.h | 9364 #define mmRLC_CGCG_CGLS_CTRL 0x4c49
[all...] |
