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    Searched refs:mmRLC_CNTL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c 2465 tmp = RREG32(mmRLC_CNTL);
2467 WREG32(mmRLC_CNTL, rlc);
2474 orig = data = RREG32(mmRLC_CNTL);
2478 WREG32(mmRLC_CNTL, data);
2488 WREG32(mmRLC_CNTL, 0);
2496 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
amdgpu_gfx_v7_0.c 3406 tmp = RREG32(mmRLC_CNTL);
3408 WREG32(mmRLC_CNTL, rlc);
3415 orig = data = RREG32(mmRLC_CNTL);
3421 WREG32(mmRLC_CNTL, data);
3479 WREG32(mmRLC_CNTL, 0);
3495 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
amdgpu_gfx_v10_0.c 1804 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1807 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
2193 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4009 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
amdgpu_gfx_v8_0.c 5549 rlc_setting = RREG32(mmRLC_CNTL);
5560 data = RREG32(mmRLC_CNTL);
5588 data = RREG32(mmRLC_CNTL);
amdgpu_gfx_v9_0.c 4442 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1138 #define mmRLC_CNTL 0x30C0
gfx_7_0_d.h 1242 #define mmRLC_CNTL 0x30c0
gfx_7_2_d.h 1255 #define mmRLC_CNTL 0x30c0
gfx_8_0_d.h 1344 #define mmRLC_CNTL 0xec00
gfx_8_1_d.h 1347 #define mmRLC_CNTL 0xec00
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h 51 { 0x00000000, mmRLC_CNTL },
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 5960 #define mmRLC_CNTL 0x4c00
gc_9_1_offset.h 6182 #define mmRLC_CNTL 0x4c00
gc_9_2_1_offset.h 6146 #define mmRLC_CNTL 0x4c00
gc_10_1_0_offset.h 9270 #define mmRLC_CNTL 0x4c00
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