HomeSort by: relevance | last modified time | path
    Searched refs:mmRLC_LB_CNTL (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si.c 112 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
159 mmRLC_LB_CNTL, 0xffffffff, 0x800000a4,
296 mmRLC_LB_CNTL, 0xffffffff, 0x80010014,
381 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4,
amdgpu_gfx_v7_0.c 3364 tmp = RREG32(mmRLC_LB_CNTL);
3369 WREG32(mmRLC_LB_CNTL, tmp);
3556 WREG32(mmRLC_LB_CNTL, 0x80000004);
amdgpu_gfx_v9_0.c 1756 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
1805 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
amdgpu_gfx_v6_0.c 2544 WREG32(mmRLC_LB_CNTL, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1150 #define mmRLC_LB_CNTL 0x30C3
gfx_7_0_d.h 1258 #define mmRLC_LB_CNTL 0x30d9
gfx_7_2_d.h 1271 #define mmRLC_LB_CNTL 0x30d9
gfx_8_0_d.h 1365 #define mmRLC_LB_CNTL 0xec19
gfx_8_1_d.h 1368 #define mmRLC_LB_CNTL 0xec19
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 6000 #define mmRLC_LB_CNTL 0x4c19
gc_9_1_offset.h 6222 #define mmRLC_LB_CNTL 0x4c19
gc_9_2_1_offset.h 6186 #define mmRLC_LB_CNTL 0x4c19
gc_10_1_0_offset.h 9308 #define mmRLC_LB_CNTL 0x4c19
    [all...]

Completed in 236 milliseconds