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    Searched refs:mmRLC_LB_CNTR_MAX (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si.c 111 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
158 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
295 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000,
380 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800,
amdgpu_gfx_v9_0.c 1726 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1727 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
1775 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
1776 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800);
amdgpu_gfx_v6_0.c 2545 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
amdgpu_gfx_v7_0.c 3550 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 1152 #define mmRLC_LB_CNTR_MAX 0x30C5
gfx_7_0_d.h 1259 #define mmRLC_LB_CNTR_MAX 0x30d2
gfx_7_2_d.h 1272 #define mmRLC_LB_CNTR_MAX 0x30d2
gfx_8_0_d.h 1366 #define mmRLC_LB_CNTR_MAX 0xec12
gfx_8_1_d.h 1369 #define mmRLC_LB_CNTR_MAX 0xec12
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 5988 #define mmRLC_LB_CNTR_MAX 0x4c12
gc_9_1_offset.h 6210 #define mmRLC_LB_CNTR_MAX 0x4c12
gc_9_2_1_offset.h 6174 #define mmRLC_LB_CNTR_MAX 0x4c12

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